Device, method and system for transparently changing a frequency of an interconnect fabric

ABSTRACT

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 17/440,688,filed Sep. 17, 2021, which is a National Stage Entry of, and claimspriority to, PCT Patent Application No. PCT/US2020/034346, filed on May22, 2020 and titled “DEVICE, METHOD AND SYSTEM FOR TRANSPARENTLYCHANGING A FREQUENCY OF AN INTERCONNECT FABRIC,” which claims thebenefit of priority to U.S. Provisional Patent Application No.62/852,948, filed May 24, 2019 and titled “Apparatus and Method to allowparallel platform and processor wakeup from deep sleep; to optimizebattery life in a processor; to prevent processor wakeup in a log sleepduration due to temperature changes, for accurate measurement andreporting of sleep state exit latency, for maximal current forintegrated regulator using dynamic voltage control; and for seamless I/Odevices interconnect fabric frequency transition,” which are hereinincorporated by reference in its entirety

TECHNICAL FIELD

This disclosure generally relates to integrated circuits and moreparticularly, but not exclusively, to managing a delivery or consumptionof power with a processor.

BACKGROUND ART

Advances in semiconductor processing and logic design have permitted anincrease in the amount of logic that may be present on integratedcircuit devices. As a result, computer system configurations haveevolved from a single or multiple integrated circuits in a system tomultiple hardware threads, multiple cores, multiple devices, and/orcomplete systems on individual integrated circuits. Additionally, as thedensity of integrated circuits has grown, the power requirements forcomputing systems (from embedded systems to servers) have alsoescalated.

Furthermore, software inefficiencies, and its requirements of hardware,have also caused an increase in computing device energy consumption. Infact, some studies indicate that computing devices consume a sizeablepercentage of the entire electricity supply for a country, such as theUnited States of America. As a result, there is a vital need for energyefficiency and conservation associated with integrated circuits. Theseneeds will increase as servers, desktop computers, notebooks,Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc.,become even more prevalent (from inclusion in the typical computer,automobiles, and televisions to biotechnology).

BRIEF DESCRIPTION OF THE DRAWINGS

The various embodiments of the present invention are illustrated by wayof example, and not by way of limitation, in the figures of theaccompanying drawings and in which:

FIGS. 1A, 1B illustrate functional block diagrams each showing featuresof a respective device to regulate communication via an interconnectfabric according to a corresponding embodiment.

FIG. 2 illustrates a flow diagram showing features of a method to changea frequency of an interconnect fabric according to an embodiment.

FIG. 3 illustrates a timing diagram showing signals which are variouslycommunicated to facilitate the changing of a frequency of aninterconnect fabric according to an embodiment.

FIG. 4 illustrates a functional block diagram showing features of asystem to determine a delivery of power to a processor according to anembodiment.

FIG. 5 illustrates a flow diagram showing features of a method to managepower delivery with a voltage regulator according to an embodiment.

FIG. 6 illustrates a functional block diagram showing features of asystem to determine a latency of a power state transition by a processoraccording to an embodiment.

FIG. 7 illustrates a timing diagram showing a sequence of events totransition a processor between power states according to an embodiment.

FIG. 8 illustrates a flow diagram showing features of a method to changea power state of a processor according to an embodiment.

FIG. 9 illustrates a functional block diagram showing features of asystem to negotiate power utilization by multiple integrated circuitchips according to an embodiment.

FIG. 10 illustrates a flow diagram showing features of a method todetermine a utilization of power by multiple integrated circuit chipsaccording to an embodiment.

FIGS. 11A-11D illustrate swim lane diagrams each showing communicationsto manage power distribution to integrated circuit chips according to acorresponding embodiment.

FIG. 12 illustrates a functional block diagram showing features of asystem to manage a delivery of power to a processor according to anembodiment.

FIG. 13 illustrates a flow diagram showing features of a method toprovide power to a processor based on a thermal condition according toan embodiment.

FIG. 14 illustrates a functional block diagram showing features of asystem to selectively determine a repository which is to store state ofa processor according to an embodiment.

FIG. 15 illustrates a flow diagram showing features of a method toselectively store processor state to one of multiple available memoryresources according to an embodiment.

FIG. 16 illustrates a graph diagram showing features of powerconsumption information which is used to determine a storing ofprocessor state according to an embodiment.

FIG. 17 illustrates a functional block diagram showing features of asystem to regulate a power state transition of a processor according toan embodiment.

FIG. 18 illustrates a flow diagram showing features of a method totransition a processor between power states according to an embodiment.

FIG. 19 illustrates a timing diagram showing a sequence of operations toperform a power state transition of a processor according to anembodiment.

FIG. 20 illustrates a functional block diagram showing features of acomputer system to manage power consumption by a processor according toan embodiment.

DETAILED DESCRIPTION

Fabric is interconnect hardware (HW) for connecting multiple blocks(e.g., logic circuit blocks) to a dedicated destination (e.g., accessmain memory). Fabric latency and bandwidth (BW) characterizationdetermine influence on the performance and Quality-of-service (QoS) ofthe system. Fabric operating frequency is a meant for the fabric BWcapabilities. A tradeoff between supplying the required BW vs. theconsumed power requires a dynamic change in frequency operating point.Fabric frequency transition effects multiple agents using the fabric fortheir normal operation. A seamless transition is required to allowfrequency transition while allowing non interruptible execution for theconnected agents. A non-negotiable transition is required to allow BWsatisfaction at any condition. A responsive switch is required to allowimmediate transition to peak BW. Past generations fabric frequencytransition intrusively involved the fabric agents. As such, the fabricfrequency transition forced the agents to stop using the fabric,draining all the outstanding traffic and included interaction with thecentral power management unit. Such fabric frequency transition isintrusive to activity of the system, results in lower performance andslow transition, and is complex as it involves multiple domains.

Some embodiments allows a fabric frequency change w/o interacting withthe agents that are connected to the fabric. All the agents have anasynchronous clock crossing between an internal clock of the agent and aclock of the fabric. The clock change is glitch free controlled by aglobal agent while the fabric agents oblivious to the clock change. Theembodiments allow for seamless frequency transition on a fabric thatallows mitigating power vs. performance tradeoffs by implementing afabric traffic band width tracer. As such, the frequency of the fabricis kept at the level required for supplying the agent traffic bandwidth.

External voltage regulator area and cost are sensitive to the maximalcurrent it may support. Modern CPU performance is limited by powerdelivery cost and area and by reducing the required currents, a CPU mayincrease its performance. One way to solve this issue is to use fixedinput voltage for an integrated buck voltage regulator. Another way isto use dynamic input voltage control that ensures minimal functionalvoltage for the regulator to minimize stress on the regulators. Thesesolutions, however, may not take advantage of the face that a buckregulator reduces its input current when the input voltage increases.

Some embodiments describe a hardware and/or software solution thatchanges the voltage determination policy by including a scheme thatincreases the input voltage to reduce the consumed current. This may bedone in order to make sure the external regulator current is within thecapability. Such implementation allows increased frequency with a samepower delivery solution.

In order to save power, when a CPU is idle, the CPU is sent by the OS(operating system) to a sleep state (e.g., package C state). The depthof the sleep state is determined by the latency of the exit time, amongother factors. The deeper the sleep state is, the more amount of powercan be saved. The CPU needs to comply with the OS and devices'advertised latency tolerance. Therefore, it is desirable to be able toaccurately measure the exit latency from a given sleep state. Inaddition, this latency can be reported back to the OS for the OS to beable to take informative decisions regarding the sleep state it chooses.

In some embodiments, each agent in the CPU that has a wake capability(e.g., Universal Serial Bus (USB) controller that can be woken up by amouse move) logs on a local clock the time it received the wakeindication. Upon a full wakeup, the CPU (or system-on-chip SoC) willquery the agent to understand how much time has passed on the agentlocal clock since the wakeup request. This is added to the SoC wakeuptime, and may be reported back to the OS.

By taking the actual latency instead of the worst case one, theapparatus and method of various embodiments are able to provide atighter measurement of the sleep state latency, and therefore reduce theworst case exit latency. Reduced sleep state exit latency leads to moretime spent in deeper sleep states, which leads to a reduced power andimproved battery life.

Existing power delivery solution are often restricted by hard limits(that must not be exceeded). This may include maximum power due tobattery capability limitation (e.g., PL4 in Intel architectures) orvoltage regulator maximal current capability. Complying with theselimits may require lowering a CPU performance (for example frequencyreduction). In some cases, these limitations may restrict a single powerdomain which includes logic circuits that are controlled by differentpower management agents. For example, a rail which is shared acrosschip-lets. At runtime, each power management agent (PMA) may require,for the respective logic circuit it controls, a lesser amount than theoverall potential may use. For example, an agent may potentially run atfrequency f_(actual)<f_(max). In this case, freeing up the unused“budget” and transferring it to circuit logic controlled by one PMA mayincrease the performance of the circuit logic controlled by another PMA.

Existing power delivery implementation may also include power featureswhich are constrained by a maximal power or current capability. This mayinclude switching to a lower power state or to an auxiliary rail. Incase that the limitation spans across more than one PMA, there is a needto restrict all PMAs in a way that the sum of each PMA limit do notexceed the overall limit.

One way to solve the above problem is to use non-blocking maximumcurrent or power interfaces. This may include notification for a futureevent (e.g., tracking of battery state of change and lowering of maximumpower). Another way to solve the above problem is to use blockinginterfaces with a single PMA. However, notification for a future eventcannot support fast changing of the limitations, and is prone to issuesdue to timing assumptions of the flows. Further, blocking interfacescannot span to topologies covering more than a single power managementdomain.

In some embodiments, maximal power or current transfer between twoagents is achieved by a request and acknowledgement interface betweentwo agents (or an acknowledgement without a corresponding request). Therequest signifies the requested or allocated maximum power/currentbudget (e.g., depending on which use case). The acknowledgementsignifies that the receiver has fulfilled all the required action tocomply with the new limitation (or to another value supplied by theacknowledgement). Once the acknowledgement is observed by the initiator,it knows that it can safely preform actions based on the new level ofthe receiving side. In some examples, the flow is blocking for a budgetincrease and may not be blocking for budget reduction.

Such mechanism allows hard limit breakdown between several componentswithin a single SoC (like budget transfer between processor cores in amulti-core design), between chip-lets (like CPU and PCH). Also, thismechanism allows a PMA controlling a voltage regulator to initiate aflow that enters a deeper power state in a safe manner, without concernsthat other consumers may require higher capabilities. Such mechanism maybe also extended to a software/firmware or software/hardware to allowcomplicated platform enabling.

When the processor going to a deep sleep state, there are still somevoltage rails that need to provide power supply that are required forthe maintenance of the operation of the processor. The power deliveryelement that delivers the voltage and current to this rail is used tooperate at its optimal working point to reduce the power even more. Tomaintain a working point, an estimation of the maximum (max) currentbeing drawn by the processor from the power delivery element is desired.The more accurate this estimation is, the better the efficiency of thepower delivery element is, and therefore—its power is lower.

Maximal drawn current is heavily dependent on the temperature of theprocessor. When the temperature is lower, leakage is reduced, hencepower requirements are reduced. However, when processor goes into a deepsleep state, it does not track the temperature. Moreover, a processor(e.g., CPU) can go to sleep at a given temperature, and heat up fromthat point by e.g., taking it out of an air conditioned room and into ahot ambient temperature. One way to mitigate issues related to hightemperature in sleep state is to consider a worst case temperature of ageneral processor specification to be 125 deg C. at design time forsleep state to able to handle cases in which the processor heats upwhile it is at sleep state. Alternatively, the processor can wake upfrequently (e.g., every few seconds) to make sure temperature is withinthe required limit. Worst case temperature based solution yields worstcase current requirement, which usually places the power deliveryelement in a non-optimal conditions, hence increases power consumptionfrom the power delivery element and the processor. Alternatively, if aprocessor is waking up frequently, each wakeup requires many resourcesto be up and running, including the power supply unit, and possible theplatform fan. This solution results in both power consumption andacoustic noises. Therefore, to be able to accurately estimate currentrequirements, the temperature is desired to be monitored by an externalagent, and power delivery element is desired to be adapt to the newoperating (e.g., temperature) conditions.

Some embodiments define a manager (software or hardware) of the powerdelivery element that uses minimum set of resources, and a temperaturemeasurement element that can generate a wake interrupt to the manager ofthe power delivery element. Power delivery manager program the thermalmonitor element to some thresholds. When the thermal element crossesthese thresholds, it wakes up the power delivery manager, which in turnchanges the working conditions of the power delivery element. As such,the processor can be put to long periods of sleep without degradingpower.

In a sleep state, voltage rails used by processor (e.g., CPU) componentsmay be removed. For example, power supply to the rails is cut off. Whena voltage rail is removed, the CPU is required to save the content thatused to reside on the voltage rail, so it can be restored later on whenthe CPU wakes up. The content can be saved in an internal memory withinthe CPU, often SRAMs (static random access memory) that operate on avoltage rail that is not removed (e.g., is powered on). Alternatively,the content can be stored to an external memory (e.g., outside of theprocessor component) by the CPU, in sleep states in which the memorycontent remains valid across sleep states. Saving to local SRAM isquicker than storing to external memory, but the SRAMs consume power.Selecting a right destination for saving the content is a function ofpower dissipation of the SRAMs, energy required to write/load memorycontent, and how often the operation is being done.

One way to select the right destination for saving the content is tostatically select (e.g., at boot time) whether to always write contentto external memory, or to avoid writing to external memory and keep thecontents in the local SRAM. However, such static selection issub-optimal in terms of energy consumption, and results in reducingbattery life.

In some embodiments, at pre-silicon time, power consumption of theinternal SRAM array and energy for writing and restoring from anexternal DRAM is characterized. In some embodiments, a mechanism isimplemented in the CPU to select whether to save content to the internalSRAM or the external DRAM based on the above parameters, and theexpected wakeup time.

When a processor (e.g., a CPU) is not fully utilized, in order to savepower, it is placed in a sleep state (e.g., package C state). In a deepsleep state, there can be some processor voltage rails that are turnedoff using a power gate that is placed on the platform mother board. Toallow proper operation when the processor is woken up, the rail needs tobe turned on. Opening a platform power gate consumes time. Time varieswith the quality of the components, and it is OEM (original equipmentmanufacturer) tradeoff between cost and latency. The latency of thepower gate impacts how fast the processor will wake-up from the sleepstate. Low wake up latency is desired to make sure the processor can goin and out of the sleep states often, in order to reduce power. Whenplatform power gates are used, processor may have to wait until theplatform power gate is open to begin its wakeup process.

Some embodiments describe apparatus and method to wake up a processorfrom a sleep state together with opening the platform power gate. Insome embodiments, the processor wait for the power gate to be fully openjust immediately prior to using this voltage rail in the processor. Theapparatus allows for parallel wakeup of the processor (e.g., CPU) andplatform rail, it allows OEMs to place inexpensive power gates, whichcan have increased latency characteristics, since the wakeup latencywill be in parallel to the CPU exit latency. This reduces BOM(bill-of-material) cost for the OEM without any impact on power orperformance.

Transitioning a Frequency of an Interconnect Fabric

Usage of an interconnect fabric (such as primary scalable fabric, or“PSF”) by a CPU typically changes at runtime with a wide range ofrequired operating bandwidth. In order to optimize the system powerwhile satisfying the performance and quality of service the PSFfrequency is changed at run time. For optimized frequency selectionnon-blocking activity is enabled and allows high transition rates.

In some embodiments, a power management (PM) unit in a CPU interactswith a clock control unit to stop a fabric clock while agents coupled tothe fabric are running on a glitch free manner. A clock provided tonodes of the fabric stops for some number of clock cycles—e.g., 4cycles—and then continues in a new frequency while the agents areunaware of the transition. Such a fast clock switch uses specific clockdividers for the desired frequencies, in some embodiments. Additionallyor alternatively, a PM unit detects at runtime the traffic over thefabric and signals a clock controller to set a fabric clock frequency totrack the desired traffic in a tight manner, which (for example) allowsfor low frequency, low power when the traffic is low, and high frequencyhigh power only when the traffic is high. The superfast frequencytransition allows a tight control over the fabric traffic.

FIG. 1A shows features of a device 100 to regulate communication via aninterconnect fabric according to an embodiment. Device 100 is oneexample of an embodiment wherein one or more integrated circuit (IC)chips comprise component devices—e.g., including, for example, any ofvarious switches, bridges, or routers—which are interconnected with eachother as a network of nodes that facilitate communication between endpoint devices. Some or all of the nodes operate based on a clock signalwhich is provided to regulate communication in the network. Variousembodiments transition such a clock signal between two frequencies,wherein the transition is transparent to one or more end point devices.

The term “interconnect fabric” (or, for brevity, “fabric”) is usedherein to refer to a network of interconnected nodes that variouslyprovide functionality for switched communication between various ones ofa processor core, memory controller, cache, PCIE I/O circuit and/orother such end point devices. As used herein, “end point device” refersto a device which is coupled to a fabric, and which is operable to serveas a source and/or a target of a communication that is performed atleast in part with the fabric. “Agent” is also used herein, in thecontext of frequency transitions of a fabric, to refer to an end pointdevice which is coupled to such a fabric.

As shown in FIG. 1A, device 100 comprises a fabric 110 which includesone or more nodes 116 which are coupled to provide switchedcommunication between various end point devices (e.g., including theillustrative agents 120, 122 shown). Some or all such end point devicesare each coupled to fabric 110 via a respective asynchronous devicewhich is to function as an asynchronous clock crossing element between afirst clock domain of fabric 110 and another clock domain which includesthe end point device in question. For example, fabric 110 comprisesasynchronous ports 112, 114 by which agents 120, 122 (respectively) arecoupled to fabric 110. Such an arrangement of asynchronous ports 112,114 facilitates a frequency change of a clock domain which includes theone or more nodes 116, without requiring agents 120, 122 to stop orotherwise modify communication processes that would otherwise beperformed in the absence of such a frequency change.

For example, device 100 further comprises a clock controller 130 whichis coupled to provide a clock signal 132 to the one or more nodes 116.Based on clock signal 132, the one or more nodes 116 participate incommunications between two or more end point devices—e.g., includingcommunications with agent 120 via asynchronous port 112 and/orcommunications with agent 122 via asynchronous port 114. Suchcommunications take place while the two or more end point devices eachoperate according to a respective clock signal other than clock signal132—e.g., wherein a first clock domain comprises the one or more nodes116, and a second clock domain comprises agent 120.

In one such embodiment, clock controller 130 provide functionality tochange a frequency of the first clock domain while a frequency of thesecond clock domain remains unchanged. By way of illustration and notlimitation, device 100 further comprises a power manager 140 which iscoupled to receive a signal 142 which specifies or otherwise indicatesthat a power state transition of device 100 is to be performed, wherethe power state transition includes or is otherwise based on a change tothe frequency of the first clock domain. Signal 142 is provided by anyof a variety of sources which are internal (or alternatively, external)to device 100—e.g., wherein generation of signal 142 includes one ormore operations which, for example, are adapted from conventional powermanagement techniques for initiating a power state transition. Someembodiments are not limited to a particular source from which signal 142is received by power manager 140, or a particular basis on which signal142 is generated.

Based on signal 142, power manager 140 participates in a communication144 of one or more signals to change a frequency of clock signal 132.For example, power manager 140 communicates to clock controller 130 acontrol signal which indicates that the first clock domain is to betransitioned from the first frequency to a second frequency. In responseto such a control signal, clock controller 130 stalls clock signal132—that is, stops a cycling by clock signal 132—for the duration of afirst period of time which (for example) is greater than a duration ofthree cycles of a lower one of the first frequency or the secondfrequency. In various embodiments, such stalling of the clock signalallows for a multiplexing or other switching between two clock dividers(or other suitable circuitry) that each correspond to a differentrespective one of the first frequency or the second frequency.

After the first period of time has expired, clock controller 130 beginsto cycle clock signal 132 at the second frequency. Since agent 120 iscoupled to the one or more nodes 116 via asynchronous port 112 (and orsince agent 122 is coupled to one or more nodes 116 via agent 122), thefrequency change to the first clock domain is transparent to some or allend point devices coupled to fabric 110. For example, agent 120 is to beable to communicate with asynchronous port 112 throughout the firstperiod of time, and/or agent 122 is to be able to communicate withasynchronous port 114 throughout the first period of time. In one suchembodiment, one or both of asynchronous ports 112, 114 are bufferedasynchronous ports to variously receive and buffer data during the firstperiod of time.

FIG. 1B shows features of a device 150 to regulate a frequency of aninterconnect fabric according to another embodiment. Device 150 is oneexample of an embodiment wherein one or more IC chips multipleinterconnect fabrics are variously coupled to one another and tomultiple end point devices, wherein control circuitry providesfunctionality to variously perform respective frequency transitions ofthe fabrics. The various frequency transitions are independent of eachother, for example, and are transparent to some or all end point deviceswhich are coupled to the fabrics. Device 150 includes some or allfeatures of device 100, for example.

As shown in FIG. 1B, device 150 comprises fabrics 160 a, 160 b, 160 cand various end point devices coupled thereto. By way of illustrationand not limitation, asynchronous ports 162 a of fabric 160 a facilitatecoupling of fabric 160 a to one or more end point devices (such as theillustrative agent 170 a shown) and to each of fabrics 160 b, 160 c.Furthermore, asynchronous ports 162 b of fabric 160 b similarlyfacilitate coupling of fabric 160 b to various agents 170 b and tofabric 160 a, wherein asynchronous ports 162 c of fabric 160 c variouslycouple fabric 160 c to agents 170 c and to fabric 160 a.

In the example embodiment shown, agent 170 a is coupled to communicatewith some or all of agents 170 b via fabrics 160 a, 160 b, and isfurther coupled to communicate with some or all of agents 170 c viafabrics 160 a, 160 c. Alternatively or in addition, a given one ofagents 170 b is coupled to communicate with some or all of agents 170 cvia each of fabrics 160 a, 160 b, 160 c. However, the particular numberand arrangement of fabrics 160 a, 160 b, 160 c—and the particular numberand arrangement of agents 170 a, 170 b, 170 c—is merely illustrative ofone embodiments. Other embodiment have any of a variety of combinationsof more, fewer, and/or differently configured fabrics and/or end pointdevices.

In one such embodiment, a first clock domain, including one or morenodes (not shown) of fabric 160 a, is provided with a clock signal 182 afrom a clock controller 180 of device 150. Similarly, clock controller180 provides other clock signals 182 b, 182 c for (respectively) asecond clock domain of fabric 160 b, and a third clock domain of fabric160 c.

Clock controller 130 provides functionality to selectively change therespective frequencies of some or all of clock signals 182 a, 182 b, 182c—e.g., responsive to power management circuitry (PM) 190 that, forexample, corresponds functionally to power manager 140. By way ofillustration and not limitation, PM 190 is coupled to receive a signal192 which specifies or otherwise indicates that a power state transitionof device 100 is to be performed, where the power state transitionincludes or is otherwise based on one or more of clock signals 182 a,182 b, 182 c each being subjected to a respective frequency change.

Based on signal 192, power manager 190 participates in a communication194 of one or more signals to facilitate the one or more frequencychanges. For example, for a given one of clock signals 182 a, 182 b, 182c, power manager 140 communicates to clock controller 130 a controlsignal which indicates that the clock signal is to be transitioned fromthe current frequency to a next frequency. In response to such a controlsignal, clock controller 130 stalls the clock signal in question, thestalling for a predetermined period of time which is greater than aduration of three cycles of a lower one of the current frequency or thenext frequency. After an expiration of the predetermined period of time,clock controller 130 begins to cycle that clock signal at indicate nextfrequency. In one such embodiment, one of clock signals 182 a, 182 b,182 c is subjected to a frequency change while respective frequencies ofthe others of clock signals 182 a, 182 b, 182 c remain unchanged. Atsome other time during operation of device 150, a different one (and,for example, only one) of clock signals 182 a, 182 b, 182 c is similarlysubjected to a frequency change which is transparent to agents 170 a,170 b, 170 c.

FIG. 2 shows features of a method 200 to change a frequency of aninterconnect fabric according to an embodiment. Method 200 is oneexample of an embodiment wherein a clock domain, which includes nodes ofa fabric, is subjected to a frequency change that is transparent to oneor more end point devices that are coupled to the fabric. Method 200 isperformed with circuitry which provides functionality of one of devices100, 150 (for example).

As shown in FIG. 2 , method 200 comprises (at 210) providing a clocksignal to one or more nodes of an interconnect fabric—e.g., wherein theproviding includes clock controller 130 providing a first frequency ofcycling by a clock signal 132 which is sent to fabric 110. Method 200further comprises (at 212) the one or more nodes communicating with anend point device based on the clock signal, wherein the end point deviceis coupled to the interconnect fabric via an asynchronous device. Theasynchronous device comprises an asynchronous buffered (oralternatively, unbuffered) port of the fabric, for example. In anembodiment, the communicating at 212 takes place while the one or morenodes operate in a first clock domain (based on the clock signal whichis provided at 210), and while the end point device operates in a secondclock domain based on a different clock signal.

Method 200 further comprises (at 214) detecting that the first clockdomain is to be transitioned from a first frequency to a secondfrequency—e.g., wherein the detecting includes or is otherwise based oninformation such as that which is communicated to power manager 140 viasignal 142. Based on the detecting at 214, method 200 further performs(at 216) stalling the clock signal throughout a first period of timewhich is greater than a duration of three cycles of a lower one of thefirst frequency or the second frequency. By way of illustration and notlimitation, the first period of time is equal to or less than a durationof five cycles of the lower one of the first frequency or the secondfrequency (e.g., wherein the clock signal is stalled for four cycles ofthe lower frequency).

In one such embodiment, method 200 further comprises storing a value ata mode register or other suitable circuitry of a controller (e.g., oneof clock controllers 130, 180) prior to the detecting at 214. The value,specifies or otherwise indicates the first period of time, is accessedin response to the detecting at 214, wherein the stalling at 216 isfurther based on the stored value.

After the first period of time of the stalling at 216, method 200 (at218) begins a cycling of the clock signal at the second frequency whichwas detected at 214. For example, in one embodiment wherein method 200is performed at device 100, the detecting at 214 comprises power manager140 communicating to clock controller 130 a first control signal whichincludes an identifier of the second frequency. Subsequently—e.g., afterclock controller 130 acknowledges a receipt of the first controlsignal—power manager 140 further communicates to clock controller 130 asecond control signal to trigger the stalling at 216, and the subsequentcycling at 218. In various embodiment, method 200 further comprises acommunicating by the end point device with the asynchronous deviceduring the first period of time—e.g., wherein the frequency change ofthe first clock domain is transparent to the end point device.

In various embodiments, method 200 further comprises additionaloperations (not shown) whereby different interconnect fabrics—e.g.,provided at a single IC chip or multiple IC chips—are variouslysubjected to respective frequency changes independent of eachother—e.g., where such frequency changes are transparent to end pointdevices that are coupled to communicate via the interconnect fabrics. Byway of illustration and not limitation, in various embodiments method200 further comprises providing a second clock signal to a second one ormore nodes of a second interconnect fabric which is coupled to theinterconnect fabric described above. In one such embodiment, the endpoint device is coupled to the first interconnect fabric via the secondinterconnect fabric. While the second clock signal is cycling at somethird frequency, a controller—e.g., providing functionality of clockcontroller 180—detects that a second clock domain (including the secondone or more nodes) is to be transitioned from the third frequency to afourth frequency. Based on such detecting, the controller stalls thesecond clock signal throughout a second period of time which (forexample) is greater than one period of the third frequency.Subsequently, after the second period of time, the controller beings tocycle the second clock signal at the fourth frequency.

FIG. 3 shows a timing diagram 300 illustrating signals which arevariously communicated between devices of an IC chip (or of multipleinterconnected IC chips) to change the frequency of a clock domainaccording to an embodiment. Communications such as those shown in timingdiagram 300 are performed with one of devices 100, 150 and/or accordingto method 200, for example. In the illustrative scenario shown by timingdiagram 300, communications are variously sent between a power managerand a clock controller (e.g., between power manager 140 and clockcontroller 130, respectively).

For example, the power manager communicates a signal FQ_Value 310 to theclock controller at time to, where FQ_Value 310 specifies a next targetfrequency to be provided with a fabric clock signal 340 (e.g., with oneof clock signals 132, 182 a, 182 b, 182 c). Subsequently, at a time t₁,the clock controller asserts a signal FVal_ACK 320 to acknowledge backto the power manager the target frequency which was most recentlyindicated by FQ_Value 310. At a time t₂, the power manager asserts asignal FQ_Change 330 to cause the clock controller to trigger atransition of fabric clock signal 340 from a currently implementedfrequency to the target frequency indicated by FQ_Value 310.

In response to the assertion of FQ_Change 330, the clock controller—at atime t₃—stalls fabric clock signal 340 for a period of time (t₄-t₃)which is longer than at least one cycle of the frequency prior to timet₃. In various embodiments, such stalling of the the clock signal allowsfor a multiplexing or other switching between two clock dividers (orother suitable circuitry) that each correspond to a different respectivefrequency. After the period of time (t₄-t₃) expires, the clockcontroller begins to cycle fabric clock signal 340 at the targetfrequency which was indicated by FQ_Value 310 at time t₀. At a time t₅,the clock controller asserts a signal FCh_ACK 350 to acknowledge back tothe power manager that the transition of fabric clock signal 340 to thetarget frequency has completed. In response to the assertion of signalFCh_ACK 350 at time t₅, the power manager deasserts signal FQ_Change 330at a time t₆. Finally, the clock controller deasserts signal FCh_ACK 350and at a time t₇.

Managing Two-Stage Voltage Regulation with a Processor

External voltage regulators area and cost is sensitive to the maximalcurrent it may support. Modern CPU performance is limited by powerdelivery cost and area and by reducing the required currents, a CPU mayincrease its performance. Some embodiments facilitate operation of asystem which includes: a two (or more) stage voltage conversion schemewhere the scheme has two consecutive stages where: the first stage hasdynamic set voltage capability; and the second stage regulatorefficiency profile guarantees that increasing the input voltage wouldresult in reduced input current (e.g. buck regulator). In someembodiments, the system includes an agent capable of determining thevoltage level defined by the first stage.

In some embodiments, the agent is a power management agent (PMA) that iscapable of determining the voltage level defined by the first stage.This agent can leverage the efficiency profile of the second stage, andreduce the current with increased voltage in order to consume the sameamount of power (or peak potential power) using a first stage regulatorcapable of delivering less current.

For example, an SoC with integrated buck regulators may want to supporta state with a peak potential power of 150 W when the buck minimal inputvoltage is 1.5V. This could be achieved by utilizing a first stageregulator capable of providing 100 A. However, if the integratedregulator can sustain up to, for example, 2V (assuming no increasedlosses in elevated voltage), this scenario can be supported using afirst stage regulator capable of providing 75 A. To do so, the powermanagement agent would need to identify that the target scenario cannotbe achieved by running at the minimal input voltage (since that may usemore input current) but may be supported if the voltage would have beenincreased. In some embodiments, the policy described above is applied toa fully integrated voltage regulator (FIVR).

FIG. 4 shows features of a system 400 to determine a delivery of powerto a processor according to an embodiment. System 400 is one example ofan embodiment wherein a processor is operable configure a mode of anexternal voltage regulator which delivers power to the processor—e.g.,wherein the mode is to mitigate a draw of current from the voltageregulator. In various embodiments, system 400 further includes otherfeatures of the processor 600, of one of devices 100, 150, and/or of oneor more of the systems 900, 1200, 1400 or 1700 described herein—e.g.,where system 400 is further operable to perform one or more of themethods 200, 800, 1000, 1300, 1500, 1800 described herein.

As shown in FIG. 4 , system 400 comprises a processor 410 and a voltageregulator (VR) 420 which is coupled thereto via a hardware interface 402of processor 410. Processor 410 comprises another voltage regulator VR430 which is coupled to receive a voltage 422 from VR 420, and togenerate a voltage 432 based on voltage 422. With voltage 432, power isdelivered to one or more circuit resources of VR 430, such as theillustrative load 440 shown.

VR 430 comprises any of a variety of converter circuits which aresuitable to provide an output voltage under various conditions of aninput current and/or various conditions of an input voltage. By way ofillustration and not limitation, VR 430 comprises a low drop out (“LDO”)converter circuit, a switched capacitor converter circuit, a bypassconverter circuit and/or other such circuitry which (for example) isadapted from conventional techniques for regulating a voltage to deliverprocessor power. Such conventional techniques are not limiting on someembodiments, and are not detailed herein to avoid obscuring certainfeatures of various embodiments. In some embodiments, VR 430 is a fullyintegrated voltage regulator (FIVR) of an IC chip which includesprocessor 410.

VR 420 comprises any of various buck (or other) converter circuits whichsupport operation according to any of multiple modes for deliveringpower with voltage 422. In some embodiments, given converter circuit ofVR 420 includes, or is coupled to, switch circuitry which determines amodulation (or other characteristic) of an output which is to beprovided with that given converter circuit. Alternatively or inaddition, VR 420 comprises multiple converter circuits and switchcircuitry to selectively couple a given one of the multiple convertercircuits to an output which provides voltage 422.

For example, configuring a mode of VR 420 comprises operating circuitryof VR 420 to switchedly couple one such converter circuit to processor410 and, for example, to switchedly decouple processor 410 from one ormore other converter circuit of VR 420. Alternatively or in addition,configuring a mode of VR 420 comprises configuring a type of modulationand/or other operation by a given converter circuit.

By way of illustration and not limitation, the multiple modes of VR 420include modes which each provide a different respective phase count fora multi-phase buck converter. Alternatively or in addition, the multiplemodes of VR 420 include modes which provide different respective typesof modulations including one or more types of pulse width modulation(PWM) and/or one or more types of pulse frequency modulation (PFM).Alternatively or in addition, the multiple modes of VR 420 include oneor more continuous conduction modes and/or one or more discontinuousconduction modes.

In some embodiments, operational states of VR 430 (the operationalstates to variously generate voltage 432 based on voltage 422) eachcorrespond to a respective one or more power delivery requirementsincluding, for example, a respective threshold minimum level of voltage422 and/or a respective threshold minimum current which VR 430 is todraw from VR 420. Similarly, modes of VR 420 each correspond to arespective one or more power delivery requirements including, forexample, a respective threshold maximum current which VR 420 is toprovide to VR 430.

To facilitate the delivery of power to load 440 using VR 420 and VR 430,processor 410 further comprises a power management agent (PMA) 450 whichprovides functionality to leverage an efficiency profile that isexhibited by VR 430. In an embodiment, PMA 450 identifies and exploitsan opportunity configure a mode of VR 420 to reduce electrical currentwhich is drawn by VR 430—e.g., where the reduction is associated with anincreased level of voltage 422—while continuing to satisfy one or morepower delivery requirements of VR 430. In one such embodiment, PMA 450controls a transition between modes of VR 420, where power delivered toprocessor 410 changes very little (if at all) due to the transition, butwhere the transition mitigates a risk of VR 420 exceeding a thresholdmaximum of current drawn by VR 430.

In the example embodiment shown, monitor logic 452 of PMA 450 compriseshardware and/or executing software which monitors one or more conditionsof power delivery to processor 410—e.g., including one or moreperformance characteristics of VR 430 and/or load 440. For example,monitor logic 452 is coupled to one or both of VR 430 and load 440, andregularly detects to identify one or more performance requirements of VR430, a power state (actual or expected) of processor 410, and/or thelike.

In various embodiment, monitor logic 452 receives an indication of acondition of the power delivery to processor 410. For example, monitorlogic 452 identifies a power state to which processor 410 is to betransitioned. Alternatively, monitor logic 452 identifies an opportunityto reduce a level of current drawn by VR 430 while processor 410 is toremain in a currently-implemented power state.

Based on the indication of a power delivery condition, monitor logic 452signals selection logic 454 of PMA 450 to utilize some predeterminedconfiguration state which indicates performance characteristics of VR420 and VR 430. For example, PMA 450 includes, is coupled to access, orotherwise operates based on configuration state (e.g., including theillustrative reference information 460 shown) which specifies orotherwise indicates whether a given mode of VR 430 accommodates one ormore performance requirements of VR 430. Reference information 460 isprovided, for example, by a manufacturer of one or both of processor 410and VR 420, or by a distributor, retailer, engineer or other externalagent—e.g., wherein the received reference information comprises updatedperformance characteristic information. Some embodiments are not limitedwith respect to a particular source from which, and/or mechanism bywhich, reference information 460 is provided to processor 410.

In the example embodiment shown, reference information 460 comprises atable 462 (or other suitable data structure) which modes M1, . . . , Mxof VR 420 as corresponding with respective levels V1, . . . , Vx of thevoltage 422, and also with respective threshold maximum current levelsC2, . . . , Cx which VR 420 is able to provide to VR 430. For example,during the mode M1 of VR 420, voltage 422 is provided at up to a levelV1, wherein VR 430 is able to draw current at up to a level C2. Bycontrast, during the mode Mx of VR 420, voltage 422 is provided at up toa level Vx, wherein VR 430 is able to draw current at up to a level Cx.In one such embodiment, reference information 460 further compriseslimit information 464 which specifies or otherwise indicates a minimumlevel Lv of voltage 422 that is required for operation of VR 430, and/ora minimum level Lc of current needed by VR 430 from VR 420.

In an embodiment, selection logic 454 performs an evaluation, based onreference information 460, to determine that a first mode of VR 430 iscompatible with a threshold maximum current of VR 420, whereas a secondmode of VR 430 is incompatible with the threshold maximum current of VR420. By way of illustration and not limitation, selection logic 454identifies some one or more modes of VR 420 (e.g., including the firstmode and the second mode) as satisfying a threshold minimum voltagewhich is required by VR 430 for a currently-implemented power state—oralternatively, for an expected next power state—of processor 410. Theidentified modes each correspond to a different respective current levelof a plurality of maximum current levels (such as the illustrativecurrent levels C2, . . . , Cx shown) which VR 420 is able to output.Subsequently, selection logic 454 selects the first mode, from among theidentified one or more modes, based on a determination that a firstcurrent level corresponding to the first mode is a lowest one of theplurality of current levels. Based on such an evaluation, PMA 450communicates a control signal 456 to transition VR 420 to the selectedmode.

In an example scenario according to one embodiment, load 440 requires 10Watts (WITH) of power, wherein a maximum current output that VR 420 canprovide 7 Amps (A), and wherein a minimum voltage that VR 430 needs toreceive is 1.5 Volts (V). In one such embodiment, a first available modeof VR 430 would meet the 10 WITH power requirement by providing voltage422 at 2.0 V while VR 430 draws 6 A. By contrast, a second availablemode of VR 430 would meet the 10 WITH power requirement by providingvoltage 422 at up to 1.5 V while VR 430 draws up to 8 A. Since thesecond mode risks a violation of the 7 A maximum current constraint byVR 420, selection logic 454 selects the first mode over the second mode,and control signal 456 communicates that VR 420 is to operate accordingto the selected first mode.

FIG. 5 shows features of a method 500 to manage power delivery with avoltage regulator according to an embodiment. Method 500 is one exampleof an embodiment wherein a processor accesses reference information thatdescribes one or more performance characteristics of an external voltageregulator. Based on such an access, the processor signals the externalvoltage regulator to transition to a mode of operation which, forexample, reduced a level of a current being provided to the processor.In various embodiments, method 500 is performed with circuitry whichprovides functionality of system 400.

As shown in FIG. 5 , method 500 comprises (at 510) generating a firstvoltage with a first voltage regulator of a processor, where the firstvoltage is generated based on a second voltage from a second voltageregulator which is coupled to the processor. In one such embodiment, theprocessor provides functionality of processor 410—e.g., where the firstvoltage regulator and second voltage regulator correspond functionallyto VR 430 and VR 420, for example.

Method 500 further comprises (at 512) receiving an indication of a powerdelivery condition of the processor. Receiving the indication at 512comprises identifying a power state to which the processor is to betransitioned. For example, power management circuitry or other suitablelogic of such the processor (e.g., the logic providing functionality ofmonitor logic 452) is configured to monitor one or more operational,environmental and/or other conditions of the processor. Such monitoringuses any of various techniques and/or mechanisms that, for example, areadapted from conventional power management techniques, which are notdetailed herein and are not limiting on various embodiments. Based onsuch monitoring, the logic detects a condition which exists (or isexpected to exist) during a current or future delivery of power to theprocessor and/or in the processor. For example, the logic identifies oneor more of a power state to which the processor is to be transitioned, acurrently enforced or anticipated voltage requirement, a currentlyenforced or anticipated current requirement, an opportunity to reduce alevel of current (or voltage), and/or the like.

Method 500 further comprises (at 514) accessing reference information,the accessing based on the receiving at 512, which indicates performancecharacteristics of the first voltage regulator and the second voltageregulator. The accessing at 514 comprises, for example, selection logic454 of PMA 450 accessing one or both of table 462 and limit information464. In various embodiments, method 500 further comprises receiving thereference information from an external agent—e.g., wherein PMA 450 ispreprogrammed or otherwise configured, in advance of the receiving at512, with operational parameters for one or both of VR 420, VR 430. Inone such embodiment, receiving the reference information comprisesreceiving updated performance characteristic information—e.g., whereinone or more values of table 462 and/or limit information 464 are updatedone or more times during a life cycle of system 400.

Method 500 further comprises (at 516) performing an evaluation, based onthe reference information, which determines that a first mode of thefirst voltage regulator is compatible with a threshold maximum currentof the second voltage regulator, wherein the first mode is selected overa second mode of the first VR based on the evaluation (where the firstand second modes are to variously provide the first voltage based on thesecond voltage from the second voltage regulator). For example, theevaluation determines that, of the first mode and the second mode, onlythe first mode is compatible with the threshold maximum current of thesecond voltage regulator. In one such embodiment, performing theevaluation at 516 comprises identifying a threshold minimum voltagerequirement of the first voltage regulator, and further identifyingthose available modes of the second voltage regulator which satisfy thethreshold minimum voltage requirement. Based on such identifying, method500 performs a selection of the first mode from among the identifiedavailable modes. In one such embodiment, the identified modes eachcorrespond to a different respective current level of a plurality oflevels of a current output from the second voltage regulator, whereinthe selection is based on a determination that a first current levelcorresponding to the first mode is a lowest one of the plurality ofcurrent levels.

Method 500 further comprises (at 518) signaling the second voltageregulator, based on the evaluation performed at 516, to operateaccording to a selected (“third”) mode to deliver power to the firstvoltage regulator. In one such embodiment, the indication is received at512 during a given power state of the processor, wherein the processormaintains that same power state after a transition of the second voltageregulator to the selected third mode.

Determining a Latency of a Power State Transition by a Processor

Both an operating system (OS) and devices communicate their latencyrequirements to a CPU while the CPU is up and running, and prior toentering sleep state. Such a CPU publishes its exit latency per a givensleep state to the OS and/or OEM devices, for example. This exit latencyinformation can be stored in register (e.g., model specific register(MSR)) accessible to the OS. While the CPU is at a sleep state, it needsbe able to wake up in response to a predefined trigger event. Suchevents can be triggered by a device, or internal reasons (e.g., timerthat is expired, wakeup due to temperature exceeding thresholds, etc.).If a wakeup is generated by a device connected to the CPU, e.g. USB(Universal Serial Bus) mouse click, or PCIe (Peripheral ComponentInterconnect Express) device requiring a service, the latency from thewake up event until the time this event is served is expected to meet OSand device latency requirements.

When a CPU is placed in a deep sleep state, only a minimal set ofresource is available for each wake-capable controller, in order to savepower. Such resources can be e.g., slow clock (which is often differentthan the functional clock) for periodic sampling of IO (input-output)and a low current power supply. In various embodiments, some or allwake-capable controllers are required to implement a mechanism to logwakeup times using an available clock. During the wakeup process, theCPU queries the controller that triggered the wake request for the timethat has passed since the wake request. The controller replies back tothe CPU with an answer based on common knowledge of both the CPU and thecontroller—e.g. how many cycles has passed when translated to a commonclock. CPU then finishes the wakeup process, and reports the aggregatedlatency back to the OS, according to techniques described herein.

FIG. 6 shows features of a processor 600 to determine a latency of apower state transition by a processor according to an embodiment.Processor 600 is one example of an embodiment wherein circuitry of aprocessor logs a time when an indication of a power state transition isdetected, where the time is prior to an activation of other circuitry ofthe processor which is to determine a latency value. In variousembodiments, processor 600 further includes other features of one ormore of the devices 100, 150 or systems 400, 900, 1200, 1400, 1700described herein—e.g., where processor 600 is further operable toparticipate in one or more of the methods 200, 500, 1000, 1300, 1500,1800 described herein.

As shown in FIG. 6 , a hardware (HW) domain of processor 600 comprises aload circuit 610, a controller 620, and a manager 630 which arevariously coupled to one another to facilitate the identifying latencydue to operations which facilitate a power state transition. Theidentified latency is subsequently communicated to one or more processesof a software (SW) domain which is executed with processor 600—e.g., theone or more processes including the illustrative operating system (OS)640 shown.

In the example embodiment shown, load circuit 610 detects a need toperform a power state transition with processor 600. For example, loadcircuit 610 comprises any of variety of power sinks and/or circuitry tomonitor an actual or expected future power demand of such a power sink.By way of illustration and not limitation, load circuit 610 comprisescore circuit logic and/or uncore circuit logic—e.g., including some orall of an execution pipeline.

In various embodiments, load circuit 610 detects a need to perform apower state transition wherein some circuitry of processor 600 istransitioned from being disabled, to being enabled to receive timinginformation and determine a latency value based on that timinginformation. Alternatively or in addition, load circuit 610 detects aneed to perform a transition of processor 600 from a first power statewhich disables an execution of software to a second power state whichenables the execution of software.

Controller 620 coupled to receive from load circuit 610 a signal 612which indicates the detected need, wherein based on signal 612, a timelogger circuit 622 of controller 620 logs a time t0 of a communicationof signal 612. Furthermore, controller 620 generates a control signal624 to request the power state transition which is indicated by signal612.

Manager 630 comprises circuitry to manage a power state transition byprocessor 600, and to communicate to one or more software processes avalue representing the duration of at least some operations which arepart of, and/or otherwise facilitate, the power state transition. Inresponse to control signal 624, manager 630 initiates a wake-upoperation to enable functionality of a time monitor circuit 632 that isincluded in (or alternatively, is coupled to) manager 630. Time monitorcircuit 632 is operable to receive time information from one or moreresources of processor 600 and, based on such timing information, toidentify the duration of operations of a power state transition (and/oroperations which otherwise facilitate the power state transition).

At some point after the wake-up operation has been initiated, manager630 is prepared to retrieve timing information that is to be provided totime monitor circuit 632. Manager 630 then requests from controller 620an indication of the time t0 that has been logged by time logger circuit622. In one such embodiment, manager 630 sends a query to controller 620to request the indication of the time t0, wherein controller 620, basedon the query, calculates a total time between the time t0 and a time ofa communication of the query. The total time is then communicated tomanager 630 in a query response message. Alternatively, controller 620responds to the query by sending an identifier of the time t0—e.g.,wherein a common clock signal 650 is made available to both controller620 and manager 630 as a shared time reference for determining thelatency based on the identifier.

Time monitor circuit 632 computes a duration of the latency based on theindication of time t0 which is provided by time logger circuit 622—e.g.,wherein the latency comprises a first period of time from the time t0 toa transmission of control signal 624 from controller 620. In variousembodiments, manager 630 queries controller 620 for the indication ofthe time t0, wherein the latency further comprises a second period oftime during the wake-up operation, and before a communication of thequery. In some of these embodiments, the latency further comprises athird period of time from the communication of the query to acommunication of a query response which includes the indication of thetime t0. In one such embodiment, the latency further comprises a fourthperiod of time after the communication of the indication of the time t0to manager 630—e.g., where manager 630 further performs or manages oneor more other operations of the power state transition after a receiptof the indication of the time t0.

Based on the computation by time monitor circuit 632, manager 630provides to operating system 640 (and/or to one or more other executingprocesses of the software domain) a message 634 comprising a value,based on the indication of the time t0, which identifies a latency ofthe power state transition. Message 634 thus facilitates (for example)improved diagnostics for evaluating power management performance.

FIG. 7 shows a timing diagram 700 which illustrates a timing of eventsat a processor which contribute to the determining, according to anembodiment, of a latency which is associated with a power statetransition. Events such as those represented in timing diagram 700 areperformed, for example, with processor 600.

In FIG. 7 , events are shown in timing diagram 700 as variouslyoccurring over a period of time 702. For example, a signal is receivedat a time TO, the signal indicating that a power state transition of theprocessor is to be performed. In the example scenario shown, thesignal—such as the signal 612 which load circuit 610 communicates tocontroller 620—specifies or otherwise indicates that at least somecircuit resource of the processor need to undergo a wake-up process tofacilitate at least some of the power state transition. In response tothe signal, controller 620 (or other suitable circuitry of theprocessor) logs the time TO which is associated with the receiving ofthe signal.

Subsequently, at a time T1, the wake-up process of the circuit resourceis initiated—e.g., wherein manager 630 (responsive to signal 624) beginsto activate resources that are used to determine a latency value. At alater time T2, the now-active circuit resource is able to retrieve orotherwise determine a value which indicates the logged time TO. Forexample, between time T1 and time T2, manager 630 sends to controller620 a query for the time t0 which was logged by time logger circuit 622.

After time T2, the wake-up (and, for example, any other operations ofthe power state transition) has completed, where—at a time T3—a latencyvalue is identified and made available to be included in a report to anoperating system (or other suitable software agent) which is executed atthe processor. In an embodiment, the latency includes some or all of aperiod of time 720 after the initiation of the wake-up process at timeT2. Moreover, latency further comprises some or all of a period of time710 from the time T1 to the time T2.

FIG. 8 shows features of a method 800 to change a power state of aprocessor according to an embodiment. Method 800 is one example of anembodiment wherein a latency of a power state transition is determinedand communicated to an operating system. The determining of the latencytime takes into account a period of time prior to the initiating of awakeup of one or more processor resources. Method 800 is performed, forexample, with circuitry that provides functionality of processor600—e.g., wherein the power state transition includes or is otherwisebased on operations such as those shown in timing diagrams 700.

As shown in FIG. 8 , method 800 includes operations 801 and otheroperations 802 which are performed (respectively) by a first circuit andby a second circuit of a processor. In one such embodiment, the firstcircuit and the second circuit correspond functionally two controllers620 and managers 630, for example. Operations 801 comprise (at 810)receiving a signal—e.g., the signal 612 communicated from load circuit610 to controller 620—which indicates a need to perform a power statetransition with the processor. In one such embodiment, the power statetransition includes a transition of the processor from a first powerstate which disables an execution of software to a second power statewhich enables the execution of software. Operations 801 further comprise(at 812) logging a time t0 of a communication of the signal—e.g.,wherein time logger circuit 622 logs a value which specifies orotherwise indicates a time when controller 620 received signal 612.Based on the signal which is received at 810, operations 801 furthergenerate a control signal (at 814) to begin one or more operations ofthe power state transition.

For example, operations 802 comprise (at 816) initiating a wake-upoperation in response to the control signal which is generated at 814.Prior to wake-up being initiated at 816, one or more resources of thesecond circuit—e.g., resources of manager 630 which participate in thedetermining of a latency that is due to of some or all of the powerstate transition—are unable to access or otherwise determine at leastsome timing information which is needed for such determining. Theinitiating at 816 uses one or more techniques and/or mechanisms which,for example, are adapted from conventional power management technologies(which are not detailed herein and are not limiting on certainembodiments).

Operations 802 further comprise (at 818) requesting an indication of thetime t0 from the first circuitry after the wake-up operation. Forexample, the second circuit sends a query to the first circuit torequest the indication of the time t0, where (in some embodiments) thefirst circuit, based on the query, calculates a total time between thetime t0 and a time of a communication of the query. Alternatively, thefirst circuit responds to such a query by identifying the time t0,wherein the second circuit subsequently calculates a duration of aperiod of time based on the time t0.

Operations 802 further comprise (at 820) providing an operatingsystem—which is executed with the processor—a communication comprising avalue, based on the indication of the time t0, which identifies alatency of at least some portion of the power state transition. Forexample, the second circuit computes a duration of the latency based onthe indication of the time t0, wherein the latency comprises a firstperiod of time from the time t0 to a transmission of the control signalwhich is generated at 814. In various embodiments, requesting theindication at 818 comprises the second circuit sending a query to thefirst circuit, wherein the latency further comprises a second period oftime during the wake-up operation, and before the sending of the query.In one such embodiment, the latency further comprises a third period oftime from the sending of the query (at 818) to a communication of theindication of the time t0 to the second circuit. Although someembodiments are not limited in this regard, the latency furthercomprises a fourth period of time after the communication of theindication of the time t0 to the second circuit. For example, the secondcircuit further performs one or more operations of the power statetransition after a receipt of the indication of the time t0 from thefirst circuit—e.g., wherein such one or more operations are also takeninto account in the determining of the value which identifies thelatency.

Negotiating Power Delivery Between IC Chips

Some embodiments variously facilitate efficient operation of anarchitectural topology wherein respective loads of multiple IC chips arepowered by a common voltage regulator—e.g., wherein one SoC hosts anintegrated voltage regulator which is used by multiple SoCs. In somecases, the overall capability of such a system is lower than the sum ofthe maximal requirement of all the consumers. For example, Table xxxbelow illustrates various use scenarios wherein an overall systemcapability is 150 Watts (W)—for example—even though multiple consumerscan each utilize up to 100 W:

TABLE 1 Example Scenarios of Power Consumption Capability MaximumScenario Scenario Scenario Scenario #4 capability #1 #2 #3 (illegal)Consumer 1 100 W 100 W  50 W  75 W 100 W Consumer 2 100 W  50 W 100 W 65 W  75 W Sum 200 W 150 W 150 W 140 W 175 WTo avoid operation such as that illustrated by scenario #4 in Table 2,some embodiments provide an interface which facilitates communicationsto negotiate power delivery between IC chips.

FIG. 9 shows features of a system 900 to negotiate power utilization bymultiple integrated circuit chips according to an embodiment. System 900is one example of an embodiment wherein a power management unit of afirst IC chip supports communication with a power management unit of asecond IC chip, the communication to negotiate a mode of powerdistribution among multiple IC chips including the first and second ICchips. In various embodiments, system 900 further includes otherfeatures of the processor 600, of one of devices 100, 150, and/or of oneor more of the systems 400, 1200, 1400 or 1700 described herein—e.g.,where system 900 is further operable to participate in one or more ofthe methods 200, 500, 800, 1300, 1500, 1800 described herein.

As shown in FIG. 9 , system 900 comprises IC chip circuitry 920, IC chipcircuitry 950, and voltage regulator 910 which are variously coupled toone another, wherein voltage regulator 910 is coupled to variouslyprovide power to each of IC chip circuitry 920, IC chip circuitry 950via a rail 912. Two IC chips each include a different respective one ofIC chip circuitry 920 and IC chip circuitry 950—e.g., wherein one of thetwo IC chips further comprises voltage regulator 910. In anotherembodiment, voltage regulator 910 is distinct from, but coupled to, thetwo IC chips. A connection 940 is coupled between respective hardwareinterfaces 921, 951 of IC chip circuitry 920 and IC chip circuitry 950,the connection 940 to facilitate negotiation of power delivery betweenthe two IC chips.

In the example embodiment shown, a first IC chip comprises IC chipcircuitry 920, wherein a power manager 922 of IC chip circuitry 920manages power distribution to, and/or power consumption by, a loadcircuit 930 of the first IC chip. Similarly, a second IC chip comprisesIC chip circuitry 950, wherein a power manager 952 of IC chip circuitry950 manages power distribution to, and/or power consumption by, a loadcircuit 960 of the first IC chip. In some embodiments, one of first ICchip or the second IC chip comprises voltage regulator 910.

Power manager 922 comprises a monitor 928, mode logic 926, andnegotiation logic 924 to facilitate a negotiation of how power is to bedistributed between multiple IC chips including the first IC chip andthe second IC chip. Power manager 952 comprises a monitor 958, modelogic 956, and negotiation logic 954 to similarly facilitate suchnegotiation. For example, power manager 922 facilitates theidentification of power requirements and/or available power budget ofthe first IC chip, where power manager 952 facilitates theidentification of power requirements and/or available power budget ofthe second IC chip.

In some embodiments, monitor 928 comprises hardware and/or executingsoftware to evaluate performance characteristics of load circuit930—e.g., wherein monitor 928 identifies one or more metrics of (actualand/or expected) power usage by load circuit 930, and tracks one or morerequirements for, or limits on, such power usage. Mode logic 926comprises hardware and/or executing software to determine, based on theevaluating by monitor 928, whether a given power state (or otheroperational mode) of the first IC chip is required or, alternatively, isavailable to be selected based on a power demand of some external agent.Negotiation logic 924 provides functionality to communicate with such anexternal agent—e.g., where such communications facilitate thedetermining of a next power state (or other operational mode) of one ofthe first IC chip or the second IC chip.

By way of illustration and not limitation, power manager 952 similarlycomprises a monitor 958 to evaluate performance characteristics of loadcircuit 960, and mode logic 956 to determine, based on the evaluating bymonitor 958, whether a given operational mode of the second IC chip isrequired or, alternatively, available to be selected. Power manager 952further comprises negotiation logic 954 to communicate with one or moreexternal agents—wherein one of negotiation logic 924 and negotiationlogic 954 communicates, via connection 940, a power requirement, anavailable power budget and/or the like.

In some embodiments, one of power managers 922, 952 (in the illustrativeembodiment shown, power manager 922) is coupled to control a delivery ofpower by voltage regulator 910 to rail 912—e.g., wherein negotiationlogic 924 communicates one or more control signals to voltage regulator910 via the illustrative connection 914 shown. In one such embodiment,power manager 952 relies on power manager 922 to control voltageregulator 910 on behalf of the second IC chip—e.g., wherein system 900omits any path by which power manager 952 is able to control voltageregulator 910 independent of power manager 922.

In the example embodiment shown, power managers 922, 952 are coupled tohardware interface 921 and hardware interface 951 (respectively) forcommunication via connection 940. Power manager 922 participates incommunications with power manager 952 while voltage regulator 910delivers power via rail 912 to each of the first IC chip and the secondIC chip.

In an illustrative scenario according to embodiment, thesecommunications comprise a first message, sent between power managers922, 952, which indicates a first transition between modes of powerconsumption by one of the first IC chip or the second IC chip. The firstmessage is, for example, a request for approval to perform the firsttransition, or (alternatively) an acknowledgement or other notificationthat the first transition has been performed, or will be performed.

In one such embodiment, the communications further comprise a secondmessage, based on the first message, which is sent from the other ofpower managers 922, 952 (that is, from the receiver of the firstmessage) to an agent which is one of voltage regulator 910 or a thirdpower management circuit of a third IC chip (not shown). The secondmessage requests a second transition of a mode of power consumption, orof power delivery, by that agent. As variously illustrated by examplesherein, one of the first transition or the second transition isperformed (for example) based on the other of the first transition orthe second transition.

By way of illustration and not limitation, in various embodiments, thefirst message requests a confirmation that the one of power managers922, 952 is approved to perform the first transition, wherein the agentis voltage regulator 910. In one such embodiment, the communicationsfurther comprise a third message from voltage regulator 910 to the otherof power managers 922, 952, the third message to confirm a performanceof the second transition. Based on the third message, the requestedconfirmation is sent, for example, in a fourth message from the other ofpower managers 922, 952 to the one of power managers 922, 952.

In some alternative embodiments, the agent is a third power managementcircuit of a third IC chip (not shown) of system 900, wherein the secondmessage requests a performance of the second transition by the thirdpower management circuit. In one such embodiment, the communicationsfurther comprise a third message from the third power management circuitto the other of power managers 922, 952 (that is, to the receiver of thefirst message). The third message confirms a performance of the secondtransition, wherein the other of power managers 922, 952 performs athird transition of a mode of power consumption based on the thirdmessage. Based on the third message, the requested confirmation is sent,for example, in a fourth message from the other of power managers 922,952 to the one of power managers 922, 952.

FIG. 10 shows features of a method 1000 to provide power to multipleintegrated circuit (IC) chips according to an embodiment. Method 1000 isone example of an embodiment wherein power management (PM) circuitry ofone IC chip participates in communications with PM circuitry of anotherIC chip to determine a distribution of power among the multiple ICchips. In various embodiments, method 1000 is performed with circuitrywhich provides functionality such as that of system 900, for example.

As shown in FIG. 10 , method 1000 comprises (at 1010) delivering powervia a rail from a voltage regulator to respective circuits of a first ICchip and a second IC chip, wherein a first power management (PM) circuitof the first IC chip is communicatively coupled to a second PM circuitof the second IC chip. The voltage regulator, the first PM circuit, andthe second PM circuit correspond functionally to voltage regulator 910,power manager 922, power manager 952 (respectively), for example. Insome embodiments, one of the first IC chip or the second IC chipcomprises the voltage regulator.

Method 1000 further comprises (at 1012) sending, from the first PMcircuit to the second PM circuit, a first message which indicates afirst transition between modes of power consumption by the first ICchip. In some embodiments, the first message indicates that the first ICchip has performed the first transition. Alternatively, the firstmessage requests that the second PM circuit perform, or otherwisefacilitate, one or more operations to enable or otherwise avail of thefirst transition. In one such embodiment, the first message requeststhat the second PM circuit provide a power state transition of thesecond IC chip and/or facilitate a change to some other resource (e.g.,an “agent” which is one of a voltage regulator or a third PM circuit ofa third IC chip).

For example, method 1000 further comprises (at 1014) sending a secondmessage, based on the first message, from the second PM circuit to anagent which is one of the voltage regulator or a third PM circuit of athird IC chip, wherein the second message requests a second transitionof a mode of power consumption or power delivery by the agent.

In various embodiments, one of the first transition or the secondtransition is based on the other of the first transition or the secondtransition. By way of illustration and not limitation, the firstmessage—in some embodiments—requests a confirmation that the first PMcircuit is approved to perform the first transition. In one suchembodiment, the agent is a voltage regulator, wherein communicationsbetween the first PM circuit, the second PM circuit and the agentfurther comprise a third message—from the voltage regulator to thesecond PM circuit—which confirm a performance of the second transition.Such communications further comprise, for example, a fourth message—fromthe second PM circuit to the first PM circuit—which comprises therequested confirmation. In another example embodiment, the first messageconfirms a performance of the first transition by the first PMcircuit—e.g., wherein the agent is the voltage regulator, and whereinthe second transition is performed based on the first transition.

Alternatively, the agent is the third PM circuit, where (for example)the second message requests a performance of the second transition bythe third PM circuit. In one such embodiment, communications between thefirst PM circuit, the second PM circuit and the agent further comprise athird message—from the third PM circuit to the second PM circuit—whichconfirms a performance of the second transition. Based on such a thirdmessage, the second PM circuit performs a third transition of a mode ofpower consumption by the second IC chip. The communications furthercomprise (for example) a fourth message from the second PM circuit tothe first PM circuit, the fourth message comprising the confirmation.

FIG. 11A-11D shows swim lane diagrams 1100-1103 variously illustratingmechanisms to determine a distribution of power each according to acorresponding embodiment. Communications and operations such as thoseshown one or more of swim lane diagrams 1100-1103 are provided, forexample, with circuitry such as that of system 900—e.g., wherein some orall such communications and operations are performed according to method1000.

Referring now to FIG. 11A, swim lane diagram 1100 shows one example ofcommunications and operations which are variously performed with avoltage regulator VR 1110, and with power management circuits PMA1 1111,PMA2 1112 which each reside on a different respective IC chip. At abeginning of the time represented in swim lane diagram 1100, a first ICchip (which includes PMA1 1111) operates in a mode which is capable ofdrawing up to 2 Amps (A) of current. Concurrently, a second IC chip(which includes PMA2 1112) operates in a mode which is capable ofdrawing up to 6 A. Altogether, the first and second IC chips have atotal current limit of 10 A.

In FIG. 11A, swim lane diagram 1100 shows a signal 1120, sent by PMA21112 to PMA1 1111, which requests that the second IC chip be allocated acurrent budget of 10 A. In response to signal 1120, PMA1 1111 sends toVR 1110 a signal 1121 which requests that the VR 1110 transition to amode which supports a total draw of at least 12 A by the first IC chipand the second IC chip. Based on signal 1121, VR 1110 performs anoperation 1122 to transition to the requested mode, and then sends toPMA1 1111 a signal 1123 which confirms that a total of 14 A (forexample) is now supported by VR 1110. In response to signal 1123, PMA11111 sends to PMA2 1112 a signal 1124 which indicates that the second ICchip can draw up to 12 A (which is the difference between the available14 A and the up to 2 A that the first IC chip might draw). Based onsignal 1124, PMA2 1112 performs an operation 1125 to transition thesecond IC chip to a mode which is capable of drawing up to 10 A.

Referring now to FIG. 11B, swim lane diagram 1101 shows an example ofadditional or alternative communications and operations which arevariously performed with a voltage regulator VR 1130, and with powermanagement circuits PMA1 1131, PMA2 1132 which each reside on adifferent respective IC chip. At a beginning of the time represented inswim lane diagram 1101, a first IC chip (which includes PMA1 1131)operates in a mode which is capable of drawing up to 2 A of current.Concurrently, a second IC chip (which includes PMA2 1132) operates in amode which is capable of drawing up to 6 A. Altogether, the first andsecond IC chips have a total current limit of 10 A.

In FIG. 11B, swim lane diagram 1101 shows an operation 1140 performed byPMA2 1132 to transition the second IC chip to a relatively low powermode which is capable of drawing only up to 1 Amp (rather up to 6 Aunder the preceding mode). Subsequently, PMA2 1132 sends a signal 1141which informs PMA1 1131 of the decreased current utilization due tooperation 1140. Based on signal 1141, PMA1 1131 sends a signal 1142which requests that VR 1130 transition to a more power efficient modewith a lower current limit (in this example scenario, to request a totalconsumption of up to 4 A by the first IC chip and the second IC chip).Based on signal 1142, VR 1130 performs an operation 1143 to transitionto the mode requested by signal 1142, after which a signal 1144 is sentto confirm to PMA1 1131 that a total current draw of 4 A is nowsupported by VR 1130.

Referring now to FIG. 11C, swim lane diagram 1102 shows another exampleof additional or alternative communications and operations which arevariously performed with a voltage regulator VR 1150, and with powermanagement circuits PMA1 1151, PMA2 1152 which each reside on adifferent respective IC chip. At a beginning of the time represented inswim lane diagram 1102, a first IC chip (which includes PMA1 1151)operates in a mode which is capable of drawing up to 2 A of current.Concurrently, a second IC chip (which includes PMA2 1152) operates in amode which is capable of drawing up to 6 A. Altogether, the first andsecond IC chips have a total current limit of 10 A.

In FIG. 11C, swim lane diagram 1102 shows a signal 1160 which PMA1 1151sends to PMA2 1152 to indicate that the first IC chip is ready totransition to a relatively low power mode. Based on signal 1160, PMA21152 performs an evaluation, and determines that is able to perform anoperation 1161 to transition the second IC chip to a more powerefficient mode which is capable of drawing only up to 1 Amp (rather upto 6 A under the currently-implemented mode of the second IC chip). PMA21152 then sends to PMA1 1151 a signal 1162 which confirms that thesecond IC chip has transitioned to the more power efficient mode, andsecond IC chip will require only up to 1 A under said mode. Based onsignal 1162, PMA1 1151 sends to VR 1150 a signal 1163 which requeststhat the VR 1150 transition to a relatively more efficient, low powermode which supports a total consumption of up to 4 A by the first ICchip and the second IC chip. In response to signal 1163, VR 1150performs an operation 1164 to transition to the requested mode, andsends to PMA1 1151 a signal 1165 which confirms that lower power mode isnow entered.

Referring now to FIG. 11D, swim lane diagram 1103 shows one example ofcommunications and operations which are variously performed with powermanagement circuits PMA1 1170, PMA2 1171, PMA3 1172 which each reside ona different respective IC chip. At a beginning of the time representedin swim lane diagram 1103, a first IC chip (which includes PMA1 1170)operates in a mode which is capable of consuming up to 10 Watts (WITH)of power. Concurrently, a second IC chip and a third IC chip (whichinclude PMA2 1171 and PMA3 1172, respectively) each operate in arespective mode which is capable of consuming up to 20 WITH. The totalamount of power that can be delivered to the first, second, and third ICchips at any given time is limited to 50 W.

In FIG. 11D, swim lane diagram 1103 shows a signal 1180 which PMA2 1171sends to PMA1 1170, the signal 1180 to request that the second IC chipbe given a 30 WITH upper limit of power consumption. Based on signal1180, PMA1 1170 sends to PMA3 1172 a signal 1181 which requests that thethird IC chip be transitioned to a mode which supports a powerconsumption of only up to 15 WITH. Based on signal 1181, PMA3 1172performs an operation 1182 to transition the third IC chip to therequested mode. Subsequently, PMA3 1172 sends to PMA1 1170 a signal 1183which confirms that the third IC chip is currently configured to consumeonly up to 15 WITH. Based on signal 1183, PMA1 1170 performs anoperation 1184 to transition the first IC chip to a lower power mode (inthis example, one which supports a power consumption of only up to 5WITH). PMA1 1170 then sends to PMA2 1171 a signal 1185 which confirmsthat, due to the respective power mode transitions by the first IC chipand the third IC chip, the second IC chip can be allowed up to 30 WITHof power consumption. Based on signal 1185, PMA2 1171 performs anoperation 1186 to transition the second IC chip to a relatively highpower mode.

Temperature-Based Management of Power Delivery to a Processor

Some embodiments variously provided a system which controls a powerdelivery element (PD) to prevent a processor wakeup in a long sleepduration due to temperature changes. For example, such a system uses aCPU which at deep sleep loses almost all of its resources, but still hasone rail to provide a minimal power delivery—e.g., to the CPU. The PDhas several working points that are set according to the maximal currentconsumption for this rail. Selecting a work point that matches highercurrent consumption may result in a higher power consumption by the PDelement. In some embodiments, the system uses a manager of the PDxelement. The manager can communicate with both CPU and power deliveryelement. The management may use a minimal set of resources to function.In some embodiments, the system uses a programmable thermal sensor. Thethermal sensor is capable of generating an interrupt when a sensedtemperature goes up or below from a threshold in given interval. Forexample, when a sensed temperature is out of a normal range within agiven internal, an interrupt may be generated.

By way of illustration and not limitation, the precise control of apower delivery element is provided, according to some embodiments, withthe following:

-   -   (a) Just prior to entering sleep state, a CPU estimates current        requirements for each of its rails—e.g., including estimated        currents to be variously provided with a given rail x, each for        a different respective temperature range of a set of temperature        ranges for the processor. In one example, scenario, some rail x        should provide some current level I₀ for a temperature range of        0° C. to 30° C., another current level I₁ for a temperature        range of 30° C. to 60° C., yet another current level I₂ for a        temperature range of 60° C. to 90° C., and still another current        level I₃ for a temperature range of 90° C. and above.    -   (b) The CPU deliver such temperature-to-current mapping        information to the PDx element manager.    -   (c) The PDx element manager determines a current temperature of        the processor, and sets the PDx element working point according        to the current-temperature map that was delivered to it by the        CPU. It then programs a programmable thermal sensor to trigger        an interrupt if the CPU temperature goes outside of the        interval.    -   (d) The PDx element manager can remove all power delivery        resources except for an interrupt detection mechanism coming        from the programmable thermal sensor.    -   (e) If the temperature exceeds the programmed interval, the        programmable thermal sensor will wake up the PDx element        manager. The PDx element can now continue from stage (c) above.

FIG. 12 shows features of a system 1200 to manage a delivery of power toa processor according to an embodiment. System 1200 is one example of anembodiment wherein circuitry, which is external to a processor, isoperable to monitor a thermal condition of the processor and, based onsuch monitoring, to change a delivery of power to the processor whilethe processor remains in a sleep (or other low power) state. In variousembodiments, system 1200 further includes other features of theprocessor 600, of one of devices 100, 150, and/or of one or more of thesystems 400, 900, 1400 or 1700 described herein—e.g., where system 1200is further operable to participate in one or more of the methods 200,500, 800, 1000, 1500, 1800 described herein.

As shown in FIG. 12 , system 1200 comprises a processor 1210, a manager1220, a programmable thermal sensor 1230, and a power delivery circuit1240 which are variously coupled to facilitate efficient power deliveryfrom power delivery circuit 1240 to processor 1210. Power deliverycircuit 1240 is coupled to provide power to processor 1210 via a rail1250—e.g., wherein power delivery circuit 1240 comprises any of variousbuck (or other) converter circuits which support operation according toany of multiple modes for power delivery. By way of illustration and notlimitation, power delivery circuit 1240 includes some or all features ofVR 420, for example.

Processor 1210 is thermally coupled to thermal sensor 1230, whichmonitors a thermal condition of an environment which includes some orall of processor 1210. Thermal sensor 1230 is programmable—e.g., bymanager 1220—to output a signal indicating the detection of giventhermal condition which is predetermined to be of interest. In variousembodiments, system 1200 omits (but facilitates coupling to, andoperation with) one or both of processor 1210 and power delivery circuit1240. Alternatively or in addition, system 1200 comprises an integratedcircuit chip which includes two or more of processor 1210, manager 1220,power delivery circuit 1240 and thermal sensor 1230.

Manager 1220 includes, is coupled to access, or otherwise operates basedon some predetermined configuration state (e.g., including theillustrative reference information 1222 shown) which specifies orotherwise indicates a correspondence of various thermal conditions eachwith a respective mode of power delivery by power delivery circuit 1240.For example, reference information 1222 comprises a table (or othersuitable data structure), entries of which variously correspond thermalconditions T1, . . . , Tx with respective power delivery requirementsR1, . . . , Rx of processor 1210, and further with respectiveoperational modes of power delivery circuit 1240.

In the example embodiment show, reference information 1222 indicatesthat a thermal condition T1 (of an environment which includes some orall of processor 1210) corresponds to a power delivery requirement R1 ofprocessor 1210, which in turn corresponds to an operational mode S2 ofpower delivery circuit 1240. For example, the power delivery requirementR1 includes a minimum required current to be drawn by processor 1210 viarail 1250. In one such embodiment, operational mode S2 is a lowest powermode of power delivery circuit 1240 which is sufficient to accommodatepower delivery requirement R1. By contrast, as indicated by referenceinformation 1222, another thermal condition Tx of the environmentcorresponds to a power delivery requirement Rx of processor 1210 (e.g.,including a different minimum required current), which in turncorresponds to an operational mode S1 of power delivery circuit 1240.

Reference information 1222 is provided to manager 1220, for example, bya manufacturer of one or both of processor 1210 and power deliverycircuit 1240, or by a distributor, retailer, engineer or other externalagent—e.g., wherein the received reference information comprises updatedpower delivery and/or power requirement information. In an embodiment,receiving reference information 1222 comprises manager 1220 receiving avalue indicating an updated performance characteristic of one ofprocessor 1210 or power delivery circuit 1240. Some embodiments are notlimited with respect to a particular source from which, and/or mechanismby which, reference information 1222 is provided to manager 1220.

In various embodiments, reference information 1222 indicates acorrespondence of thermal conditions each with a different respectivemode of a plurality of modes of power delivery circuit 1240, wherein theplurality of modes are each to deliver power to processor 1210 during aparticular power state of processor 1210. In one such embodiment, thepower state disables an ability of processor 1210 (if any) to detect orotherwise determine whether power delivery circuit 1240 is to betransitioned between modes for variously delivering power via rail 1250.Alternatively or in addition, the power state disables softwareexecution with processor 1210, for example.

Based on reference information 1222, manager 1220 provides a signal 1224which sets a trigger condition of thermal sensor 1230—e.g., whereinsignal 1224 communicates trigger information 1232 indicating a thermalcondition which is to cause thermal sensor 1230 to interrupt, wake up orotherwise notify manager 1220. Based on trigger information 1232,thermal sensor 1230 monitors a thermal state to detect whether or notthe trigger condition indicated by trigger information 1232 has beensatisfied.

At some point during operation of system 1200, thermal sensor 1230 sendsa signal 1234 to manager 1220 in response to an indication that thetrigger condition is satisfied. For example, signal 1234 specifies orotherwise indicates a thermal condition which has been detected,wherein, based on the indicated thermal condition, manager 1220 accessesreference information 1222 to identify a corresponding mode of powerdelivery circuit 1240.

In response to signal 1234 (and based on reference information 1222),manager 1220 generates a signal 1226 to control a transition of powerdelivery circuit 1240 between two of the plurality of modes. In variousembodiments, signal 1226 operates one or more switch circuits and/orother suitable circuitry (represented as the illustrative mode setcircuitry 1242 shown) to transition power delivery circuit 1240 to arelatively more power efficient mode. In one such embodiment, the samepower state of processor 1210 is to be maintained after thetransition—e.g., wherein software execution and/or some or all powermanagement functionality at processor 1210 continues to be disabledafter the mode transition by power delivery circuit 1240.

FIG. 13 shows features of a method 1300 to provide power to a processorbased on a thermal condition according to an embodiment. Method 1300 isone example of an embodiment wherein a working point of circuitry isautomatically updated, by power management logic which external to aprocessor, to improve an efficiency with which the circuitry deliverspower to the processor while the processor remains in the low powerstate. In various embodiments, some or all of method 1300 is performedwith circuitry which provides functionality of system 1200, for example.

As shown in FIG. 13 , method 1300 comprises (at 1310) receivingreference information at circuitry which is coupled to a processor. Thereference information indicates a correspondence of thermal conditionseach with a different respective mode of a plurality of modes of a powerdelivery circuit (wherein the plurality of modes are each suitable todeliver power to the processor during the same power state of theprocessor). In various embodiments, receiving the reference informationat 1312 comprises the circuitry receiving first information, from theprocessor, which indicates a correspondence of power deliveryrequirements of the processor each with a different respective one ofthe thermal conditions. The receiving at 1312 further comprises thecircuitry receiving second information which indicates respectiveperformance characteristics of each of the plurality of modes (wheresome or all such performance characteristics each satisfy a respectiveone of the power delivery requirement at least in part).

For example, the reference information identifies multiple electricalcurrent requirements (and/or voltage requirements) of the processor aseach corresponding to a different respective thermal condition. Althoughvarious embodiments are not limited in this regard, the receiving at1310 comprises (for example) the circuitry receiving one or more valueswhich each represent or otherwise indicate a respective updatedperformance characteristic of one of the processor or the power deliverycircuit.

In an example embodiment, the processor, the circuitry, the referenceinformation, and the power delivery circuit correspond functionally toprocessor 1210, manager 1220, reference information 1222, and powerdelivery circuit 1240 (respectively). Additionally or alternatively, anintegrated circuit chip comprises both the processor and the circuitry,for example.

Based on the reference information received at 1310, method 1300 furthersets a trigger condition (at 1312) of a programmable thermalsensor—e.g., sensor 1230—which is thermally coupled to the processor.The trigger condition includes or otherwise determines a thermalcondition which, if detected, is to result in the generation of anoutput signal by the programmable thermal sensor. For example, based onmultiple electrical current (and/or voltage) requirements indicated bythe reference information, the programmable thermal sensor is set togenerate an interrupt or other message in response to the detection of athermal condition which has been identified as corresponding to aparticular one of the multiple requirements. In one such embodiment, thesetting at 1312 comprises manager 1220 communicating trigger information1232 to thermal sensor 1230 via signal 1224.

After the trigger condition is set at 1312, method 1300 further monitorsthe processor (at 1314) with the programmable thermal sensor—e.g.,including thermal sensor 1230 regularly sensing a thermal state of anenvironment which includes some or all of processor 1210. In oneembodiment, the processor remains in one power state throughout themonitoring at 1314—e.g., wherein the power state is a sleep state (orother such low power state) during which the processor is unable toindependently determine whether the power delivery circuit is totransition between modes.

Method 1300 further comprises (at 1316) sending a signal from theprogrammable thermal sensor to the circuitry in response to anindication—detected by the monitoring at 1314—that the trigger conditionis satisfied. For example, the sending at 1316 comprises thermal sensor1230 communicating signal 1234 to wake up manager 1220.

Method 1300 further comprises (at 1318) with the circuitry, controllinga transition of the power delivery circuit between two of the pluralityof modes. For example, in response to the interrupt, the circuitryidentifies a mode of the power delivery circuit which—by virtue of acorresponding power delivery requirement of the processor—corresponds tothe detected thermal condition. The power state of the processor (whichexisted during the monitoring at 1314) is maintained after thetransition—e.g., the power state disables software execution with theprocessor and/or disables any independent determination by the processoras to whether or when the power delivery circuit is to transitionbetween modes. In an example embodiment, the controlling at 1318comprises manager 1220 sending to mode set circuitry 1242 the signal1226 which identifies a new operational point with which power deliverycircuit 1240 is to deliver power to processor 1210 via rail 1250.

Selection of a Repository to Store Processor State

FIG. 14 shows features of a system 1400 to selectively determine arepository which is to store state of a processor according to anembodiment. System 1400 is one example of an embodiment wherein aprocessor is operable to dynamically estimate whether an internalresource of the processor, or some external memory resource, is likelyto be a more power efficient repository of processor state. In variousembodiments, system 1400 further includes other features of theprocessor 600, of one of devices 100, 150, and/or of one or more of thesystems 400, 900, 1200, or 1700 described herein—e.g., where system 1400is further operable to participate in one or more of the methods 200,500, 800, 1000, 1300, 1800 described herein.

As shown in FIG. 14 , system 1400 comprises a processor 1410 and amemory 1490 which is coupled thereto—e.g., via hardware interface 1405of processor 1410 and a controller 1480. Processor 1410 comprisescircuitry 1450 (e.g., including one or more registers, some or all of anexecution pipeline, and/or the like) and a memory 1470 which isavailable to store a state of circuitry 1450. In one example embodiment,memory 1470 comprises a static random-access memory (SRAM), whereinmemory 1490 comprises a dynamic random-access memory (DRAM).

Processor 1410 further comprises a detector 1420, an evaluation circuit1430, and a controller 1440 which are variously coupled to one anotherto facilitate the selective storage of processor state to a particularone of memories 1470, 1490. For example, processor 1410 furthercomprises multiplexer/demultiplexer (mux/demux) circuitry 1460 which iscoupled between circuitry 1450 and each of memory 1470 and hardwareinterface 1405. Responsive to controller 1440, mux/demux circuitry 1460is operable to communicate processor state, via a path 1462, for storageat memory 1470 or (alternatively) to communicate such processorstate—via a path 1464, hardware interface 1405, and controller 1480—forstorage at memory 1470. Mux/demux circuitry 1460 is further operable toselectively retrieve processor state to circuitry 1450 from a selectedone of memories 1470, 1490.

In the example embodiment shown, detector 1420 is coupled to receive asignal 1412 which specifies or otherwise indicates that a power statetransition of processor 1410 is to be performed. For example, signal 142indicates that processor 1410 is to be transitioned to a power statewhich does not support the maintenance of at least some processor state(represented as state information 1452) at circuitry 1450. Signal 1412is provided by any of a variety of sources which are internal (oralternatively, external) to processor 1410—e.g., wherein generation ofsignal 1412 includes one or more operations which, for example, areadapted from conventional power management techniques for initiating apower state transition. Some embodiments are not limited to a particularsource from which signal 1412 is received, or a particular basis onwhich signal 1412 is generated.

Based on signal 1412, detector 1420 identifies a predicted length oftime that processor 1410 is to be in the indicated power state. In anembodiment, determining the predicted length of time includes one ormore operations which, for example, are adapted from conventional powermanagement techniques for estimating future power demands of aprocessor. Such conventional techniques are not limiting on someembodiments, and are not detailed herein to avoid obscuring certainfeatures of various embodiments.

Evaluation circuit 1430 is coupled to receive from detector 1420 asignal 1422 which specifies or otherwise indicates the predicted lengthof time that processor 1410 is to be in the power state indicated bysignal 1412. Based on the predicted length of time, evaluation circuit1430 performs a calculation to detect a relative benefit of storingstate information 1452 to one of memories 1470, 1490 over storing stateinformation 1452 to the other of memories 1470, 1490.

For example, evaluation circuit 1430 includes, is coupled to access, orotherwise operates based on configuration state (e.g., including theillustrative reference information 1432 shown) which indicates, for eachof memories 1470, 1490, a respective one or more resource requirementsto operate the memory. Reference information 1432 is provided, forexample, by a manufacturer of one or both of processor 1410 and memory1490, or by a distributor, retailer, engineer or other externalagent—e.g., wherein the received reference information 1432 comprisesupdated performance characteristic information. Some embodiments are notlimited with respect to a particular source from which, and/or mechanismby which, reference information 1432 is provided to processor 1410.

In the example embodiment shown, reference information 1432 includes atable (or other suitable data structure), entries of which identify—forone or more of the illustrative operational parameters PA, . . . , PNshown—respective values pa1, . . . , pn1 which variously describeoperation of memory 1470. Alternatively or in addition, referenceinformation 1432 identifies, for the same and/or others of parametersPA, . . . , PN—respective values pa2, . . . , pn2 which variouslydescribe operation of memory 1490. Based on resource requirementsindicated by reference information 1432, evaluation circuit 1430performs a calculation to detect a relationship between first resourcerequirements to store processor state to memory 1470, and secondresource requirements to store processor state to memory 1490.

In various embodiments, the calculation performed by evaluation circuit1430 is based on one or more parameter values including, for example, avalue T1 indicating a length of time required to write a referenceamount of data to memory 1470, and/or a value P1 indicating an amount ofpower required to retain the reference amount of data in memory 1470.Additionally or alternatively, the one or more parameter values includea value T2 indicating a length of time required to write the referenceamount of data to memory 1490, and/or a value E2 indicating an amount ofenergy required to write the reference amount of data to memory 1490 andto read the reference amount of data from memory 1490. Additionally oralternatively, the one or more parameter values include a value Piindicating an amount of power consumed by processor 1410 during areference period of time. In one such embodiment, evaluation circuit1430 performs the calculation based on a ratio of a first value to asecond value, wherein the first value is based on the value Pi, andwherein the second value is based on the value P1. The first value, insome embodiments, is further based on a difference between the value T2and the value T1. Particular examples of such calculations are detailedin the description of method 1500 herein.

Based on the calculation, evaluation circuit 1430 provides to controller1440 a signal 1434 which identifies one of memories 1470, 1490 as apreferred repository for state information. Based on signal 1434,controller 1440 variously signals circuitry 1450 and mux/demux circuitry1460 to store state information 1452 to the selected one of memories1470, 1490. For example, controller 1440 sends a signal 1442 to indicatethat circuitry 1450 is to output state information 1452 to mux/demuxcircuitry 1460. Furthermore, controller 1440 provides to mux/demuxcircuitry 1460 a control signal 1444 which selects one of paths 1462,1464 to communicate state information 1452 to the corresponding one ofmemories 1470, 1490.

FIG. 15 shows features of a method 1500, according to an embodiment, toselectively store processor state to one of multiple available memoryresources. Method 1500 is one example of an embodiment whereinperformance characteristics of a processor are evaluated to determine,based on a predicted period of time that the processor will be in a lowpower state, whether it is more power efficient to store processor stateto local memory or to an external memory. In various embodiments, method1500 is performed with circuitry which provides functionality such asthat of system 1400.

As shown in FIG. 15 , method 1500 comprises (at 1510) receiving anindication that a transition of the processor to a power state is to beperformed, wherein the processor comprises a first memory, and wherein asecond memory is coupled to the processor. For example, the receiving at1510 comprises detector 1420 receiving the signal 1412, which specifiesor otherwise indicates that processor 1410 is to be transitioned to alow power state which is unable to maintain state information 1452 atcircuitry 1450. In one embodiment, the first memory comprises a staticrandom-access memory (SRAM) of the processor, and the second memorycomprises a dynamic random-access memory (DRAM).

Method 1500 further comprises (at 1512) identifying a predicted lengthof time that the processor is to be in the power state. For example, theidentifying at 1512 is based on signal 1412 and/or other availableinformation which is available to detector 1420, where the informationspecifies or otherwise indicates an estimated duration of the powerstate. The identifying at 1512 includes one or more operations which(for example) are adapted from conventional power management techniquesfor estimating future processor use. Such conventional techniques arenot detailed herein, and are not limiting on certain embodiments.

Method 1500 further comprises (at 1514) performing a calculation, basedon the indication and the predicted length of time, to detect a relativebenefit of storing a state of the processor to one of the first memoryor the second memory over storing the state of the processor to theother of the first memory or the second memory. For example, thecalculating at 1514 comprises evaluation circuit 1430 identifying, basedon reference information 1432, one or more values which each describe aperformance characteristic associated with a respective one of the firstmemory or the second memory.

By way of illustration and not limitation, performing the calculation at1514 is based on one or more parameters including (for example) a lengthof time required to write a reference amount of data to the firstmemory, an amount of power required to retain the reference amount ofdata in the first memory, and a length of time required to write thereference amount of data to the second memory. Alternatively or inaddition, the one or more parameters include (for example) an amount ofenergy required to both write the reference amount of data to the secondmemory and read the reference amount of data from the second memory, andan amount of power consumed by the processor during a reference periodof time.

For example, in an illustrative scenario according to one embodiment, anenergy amount Esram needed to use the first memory (e.g., a SRAM) as arepository for processor state is represented by the following equation:

Esram=[(T1)(Pi)+(P1)(Tx)],  (1)

where:

-   -   T1 represents a length of time required to write some reference        amount of data to the first memory;    -   P1 represents an amount of power required to retain the        reference amount of data in the first memory; and    -   Tx represents the predicted length of time that the processor        will be in the power state.

By contrast, an energy amount Edram needed to use the second memory(e.g., a DRAM) as a repository for processor state is represented by thefollowing equation:

Edram=[E2+(T2)(Pi)],  (2)

where:

-   -   E2 represents an amount of energy required by the memory        subsystem (external to the processor) to write the reference        amount of data to the second memory and to read the reference        amount of data from the second memory;    -   T2 represents a length of time required to write the reference        amount of data to the second memory; and    -   Pi represents an amount of power consumed by the processor        during some reference period of time.

In view of equations (1) and (2) above, it is preferable—in this examplescenario—to save processor state to the first memory (as opposed to thesecond memory) where the performing at 1514 calculates or otherwisedetects the following inequality:

[(T1)(Pi)+(P1)(Tx)]<[E2+(T2)(Pi)],  (3)

which, in turn, corresponds to the inequality below:

Tx<[E2+(T2−T1)(Pi)]/(P1).  (4)

Therefore, in some embodiments, the performing at 1514 includes one ormore calculations to detect whether a predicted length of time that theprocessor will be in the low power state is less than the ratio shown onthe right hand side of inequality (4) shown above. Accordingly, in someembodiments, the calculating at 1514 is based on a ratio of a firstvalue to a second value, wherein the first value is based on the valuePi, and wherein the second value is based on the value P1. The firstvalue is further based (for example) on a difference between the valueT2 and the value T1.

Based on the calculation performed at 1514, method 1500 (at 1516) storesthe state of the processor to the one of the first memory or the secondmemory which has been identified as a relatively more power efficientrepository of said state. In various embodiments, the calculation isperformed at 1514 identifies the inequality (4) above, wherein thestoring at 1516 comprises storing the state to the first memory. In someembodiments, method 1300 further comprises the processor receivingreference information—prior to the indication being received at1510—which indicates, for each of the first memory and the secondmemory, respective resource requirements to operate the memory, whereinthe calculation performed at 1514 is further based on the information.In one such embodiment, the reference information (e.g., including oneor more values of reference information 1432) updates the description ofone or more resource requirements to access a given one of the firstmemory of the second memory.

FIG. 16 shows a graph 1600 illustrating an amount of power 1602 which isexpected to be needed to use a given memory for storing state of aprocessor. For the given memory, the amount of power 1602 depends atleast in part on an expected amount of time 1604 that the processor willbe in a power state (a sleep state, for example) during which somecircuit resource of the processor—e.g., a resource other than aninternal memory of the processor—is unable maintain said processorstate.

Graph 1600 represents one example of information used in someembodiments—for example, used by evaluation circuit 1430 and/oraccording to method 1500—to determine whether processor state is to bestored to a local memory of the processor or (alternatively) to anexternal memory which is coupled to the processor.

As shown in graph 1600, plot 1610 represents, as a function of theexpected time 1604, an expected amount of power required for processorstate to be written to, maintained at, and read from a DRAM (at memory1490, for example) that is coupled to a processor. By contrast, plot1620 represents an expected amount of power required for processor stateto be written to, maintained at, and read from a SRAM (at memory 1470,for example) of said processor.

In the example scenario shown, graph 1600 includes a breakeven point—atan expected time duration of approximately 0.14 seconds—where noparticular power efficiency can be expected from saving processor stateto a given one of the SRAM or the DRAM. Where the expected time durationis less than the breakeven point, it is expected to be relatively morepower efficient to save processor state to the SRAM (as compared tosaving such state to the DRAM). By contrast, it is expected to berelatively more power efficient to save the processor state to the DRAMif the expected time duration is greater than the breakeven point.

Timing Operations of a Power State Transition Based on Power GateLatencies

When a processor goes into deep sleep state (e.g., package state C10),few of its rails are being power gated by a platform power gate that isimplemented by an OEM. Not all power gates have the same latencyspecification. Some rails are required for the CPU to starts its wakeupprocess—since they provide the infrastructure voltage for the wakeupprocess itself (referred to herein as belonging to a rail type of Type1), some are required for later, during the wakeup process (referred toherein as belonging to a rail type of Type 2).

Some embodiments variously facilitate a communication of a maximumlatency (Tinit) of multiple power gates that each couple to a respectiveType 1 rail, and/or communication of the respective latencies of powergates that each couple to a respective Type 2 rail. In one suchembodiment, a CPU waits for Tinit to expire before it starts an actualwaking up, and internally, during the wakeup process, it will wait for aType 2 latency to expire before using a corresponding Type 2 rails.Certain features of various embodiments are described herein withrespect to the timing of operations, by load circuits of a processor,based on different latencies of power gates that are to variouslydeliver power each to a respective one of said load circuits. However,such features can be extended to apply to embodiments which additionallyor alternatively time operations of a processor's load circuits based ondifferent latencies of voltage regulators that are to deliver power eachto a respective one of said load circuits.

FIG. 17 shows features of a system 1700 to regulate a power statetransition of a processor according to an embodiment. System 1700 is oneexample of an embodiment wherein a processor is operable to generatecontrol signals based on values which each indicate a differentrespective latency of a corresponding power gate (or, in someembodiments, a corresponding voltage regulator) that is coupled to theprocessor. The control signals are communicated each to a differentrespective load circuit of the processor, wherein the load circuitsinitiate respective operations of a power state transition at differenttimes based on the control signals. In an embodiment, the operations aretimed to accommodate the various latencies of one or more power gates.In various embodiments, system 1700 further includes other features ofthe processor 600, of one of devices 100, 150, and/or of one or more ofthe systems 400, 900, 1200, or 1400 described herein—e.g., where system1700 is further operable to participate in one or more of the methods200, 500, 800, 1000, 1300, 1500 described herein.

As shown in FIG. 17 , system 1700 comprises a processor 1730 and powergates 1720 a, 1720 b which are variously coupled thereto via a hardwareinterface 1740 of processor 1730. Processor 1730 further comprises rails1722 a, 1722 b, and load circuits 1760 a, 1760 b, wherein power gate1720 a is operable to selectively deliver power to load circuit 1760 avia rail 1722 a, and wherein power gate 1720 b is operable toselectively deliver power to load circuit 1760 b via rail 1722 b. Tofacilitate such power delivery, control logic 1710 of system 1700comprises hardware and/or executing software to generate control signals1712 a, 1712 b which variously operate power gates 1720 a, 1720 b(respectively). In various embodiments, system 1700 omits (butfacilitates coupling to, and operation with) some or all of controllogic 1710 and power gates 1720 a, 1720 b. Alternatively or in addition,system 1200 comprises an integrated circuit chip which includes two ormore of processor 1730, control logic 1710 and power gates 1720 a, 1720b.

To efficiently time multiple operations of a power state transition,circuitry 1750 of processor 1730 comprises a detector 1752, timercircuitry (in this example, comprising the illustrative timer circuits1754 a, 1754 b shown), and a signal generator 1756. The timer circuitryis operable to detect, based on the signal, a first expiration of thefirst period of time, and a second expiration of the second period oftime, wherein respective portions of the first period of time and thesecond period of time are concurrent with each other. A first period oftime and the second period of time are determined, for example, based onreference information which is used to configure timer circuits 1754 a,1754 b (respectively).

By way of illustration and not limitation, circuitry 1750 couples to (oralternatively, includes) a manager 1770 which provides functionality toconfigure timer circuit 1754 a and/or timer circuit 1754 b. For example,manager 1770 includes, is coupled to access, or otherwise operates basedon configuration state (e.g., including the illustrative referenceinformation 1772 shown) which specifies or otherwise indicates, for eachof multiple power gates including power gates 1720 a, 1720 b, arespective time required to open the power gate. Reference information1772 is provided, for example, by a manufacturer of one or both of powergates 1720 a, 1720 b, or by a distributor, retailer, engineer or otherexternal agent—e.g., wherein the received reference informationcomprises updated performance characteristic information. Someembodiments are not limited with respect to a particular source fromwhich, and/or mechanism by which, reference information 1772 is providedto manager 1770.

In the example embodiment shown, reference information 1772 comprises atable (or other suitable data structure), entries of which identify atime t0 needed to open a power gate g0, a time tx needed to open a powergate gx, and/or the like. Manager 1770 determines a first duration of afirst period of time based on a first reference value which indicates afirst latency of power gate 1720 a. Manager 1770 further determines asecond duration of a second period of time based on a second referencevalue which indicates a second latency of power gate 1720 b. Based onthe determined first duration and second duration, manager 1770communicates control signals 1774 a, 1774 b which (respectively)configure timer circuit 1754 a for detection of the first period oftime, and configure timer circuit 1754 b for detection of the secondperiod of time.

At some point during operation of system 1700, control logic 1710generates a signal 1714 which indicates that processor 1730 is toundergo a transition to a power state in which load circuits 1760 a,1760 b receive power via power gates power gate 1720 a, 1720 b(respectively). Based on signal 1714, detector 1752 sends a signal 1753a for timer circuit 1754 a to begin detecting for a first expiration ofthe first period of time. Furthermore, detector 1752 sends anothersignal 1753 b for timer circuit 1754 b to begin detecting for a secondexpiration of the second period of time.

At different times, signal generator 1756 receives from timer circuits1754 a, 1754 b respective signals 1755 a, 1755 b to variously indicatethe first expiration and second expiration. In response to signal 1755a, signal generator 1756 sends a signal 1757 a to initiate a firstoperation of the power state transition at circuit 1760 a. Similarly,signal generator 1756 sends another signal 1757 b, in response to signal1755 b, to initiate a second operation of the power state transition atcircuit 1760 b. In an embodiment, the first operation is performed withpower provided via power gate 1720 a, and the second operation isperformed with power provided via power gate 1720 b.

FIG. 18 shows features of a method 1800 to transition a processorbetween power states according to an embodiment. Method 1800 is oneexample of an embodiment wherein operations of a power state transition,the operations by various circuits of a processor, are initiated atdifferent times to accommodate the respective latencies of multiplepower gates that are to deliver power to the processor. In variousembodiments, method 1800 is performed with circuitry which providesfunctionality such as that of system 1700.

As shown in FIG. 18 , method 1800 comprises (at 1810) receiving valueswhich each indicate a different respective latency of a correspondingpower gate of multiple power gates which are coupled to the processor.The receiving at 1810 comprises (for example) manager 1770 receiving andstoring some or all data of reference information 1772. In someembodiments, the receiving at 1810 comprises storing data—communicatedto the processor by an external agent—which comprises a first value anda second value indicating (respectively) a first latency of a firstpower gate and a second latency of a second power gate. In one suchembodiment, one of the first value or the second value is to replaceanother value indicating a previous latency of one of the first powergate or the second power gate.

After receiving the plurality of values at 1810, method 1800 furtherdetects (at 1812) that a power state transition of the processor is tobe performed. Based on the detecting at 1812, method 1800 furthergenerates control signals (at 1814) which are each based on a differentrespective one or more of the values.

By way of illustration and not limitation, the multiple power gatescomprise first power gates, wherein generating the control signals at1812 comprises determining a first duration of a first period of timebased on each of first values which indicate respective first latenciesof the first power gates. In one such embodiment, the multiple powergates further comprise a second one or more power gates, whereingenerating the control signals further comprises determining a secondduration of a second period of time based on a second one or more valueswhich indicate a second one or more latencies of the second one or morepower gates. For example, the second duration is determined based alatency of only one power gate.

In one example embodiment, determining the first duration based on thefirst values includes performing a calculation with each of the firstvalues based on a determination that the first plurality of power gateseach belong to a first power gate type (e.g., a type of power gates thatare required to deliver power concurrently for at least some one or moreoperations of the power state transition). The first duration isdetermined, for example, as being equal to (or otherwise based on) amaximum of the respective first latencies of the first power gates. Bycontrast, the second one or more power gates each belong to a respectivepower gate type other than the first power gate type.

In an illustrative scenario according to one embodiment, the generatingat 1814 comprises operating timer circuitry of the processor to detect afirst expiration of a first period of time, and a second expiration of asecond period of time, wherein respective portions of the first periodof time and the second period of time are concurrent with each other.For example, the generating at 1814 includes or is otherwise based onmanager 1770 setting, for each of timer circuits 1754 a, 1754 b, arespective count limit or other suitable trigger condition.Subsequently, detector 1752 communicates signals 1753 a, 1753 b toinitiate respective counts by timer circuits 1754 a, 1754 b, whichvariously generating respective signals 1755 a, 1755 b each to indicatean expiration of a corresponding period of time.

Method 1800 further comprises (at 1816) communicating the controlsignals each to a different respective load circuit of the processor,wherein, in response to the control signals, the load circuits initiaterespective operations of the power state transition at different times.For example, the communicating at 1816 comprises signal generator 1756sending signal 1757 a, signal 1757 b to load circuit 1760 a, loadcircuit 1760 b, respectively.

In an illustrative embodiment, the communicating at 1816 comprisessignaling a first load circuit of the processor, based on a firstexpiration of a first period of time, to perform a first operation ofthe power state transition with power provided via a first power gate.Furthermore, the communicating at 1816 comprises signaling a secondcircuit of the processor, based on a second expiration of a secondperiod of time, to perform a second operation of the power statetransition with power provided via a second power gate. In one suchembodiment, the second period of time expires after the first period oftime—e.g., wherein the second operation of the power state transition isbased at least in part on a completion of at least some of the firstoperation.

FIG. 19 shows a timing diagram 1900 which illustrates respectivelatencies of power gates that deliver power to a processor according toan embodiment. In FIG. 19 , timing diagram 1900 shows how, over time1910, the power gates variously open to deliver power to the processor.Load circuits of the processor variously initiate power transitionoperations based on latencies of the power gates—e.g., wherein theinitiating is timed with circuitry of system 1700 and/or according tomethod 1800.

In the example scenario illustrated by timing diagram 1900, a processorcomprises first load circuits that initiate respective power transitionoperations once power is being variously delivered to each of said firstload circuits. The processor further comprises a second one or more loadcircuits that are each to initiate a respective power transitionoperation independent of whether power is being delivered to any otherload circuit. Table 2 below lists one example of latencies, and powergate types, for power gates which are to deliver power to such loadcircuits.

TABLE 2 Example of Power Gate Types and Latencies Power Gate Gate TypeLatency (μsec) PG1 Type 1 120 PG2 Type 1 30 PG3 Type 1 90 PG4 Type 2 180PG5 Type 3 210 PG6 Type 4 270

To facilitate a power state transition by such a processor, first powergates of a gate type 1—in this example, power gates PG1, PG2, PG3—eachcorrespond to a respective one the first load circuits, and respectivepower transition operations of the first load circuits are initiatedbased on respective latencies of the first power gates. For example, thepower transition operations of the first load circuits are eachinitiated after expiration of a time Tinit which is equal to a maximumof the respective latencies of power gates PG1, PG2, PG3. By contrast,the respective expirations of times T4, T5, and T6 (which correspond tothe respective openings of power gates PG4, PG5, and PG6) eachindependently trigger the initiation of a power transition operation bya different respective load circuit.

FIG. 20 illustrates a computer system or computing device 2000 (alsoreferred to as device 2000), where power distribution and/or powerconsumption is managed in accordance with some embodiments. It ispointed out that those elements of FIG. 20 having the same referencenumbers (or names) as the elements of any other figure can operate orfunction in any manner similar to that described, but are not limited tosuch.

In some embodiments, device 2000 represents an appropriate computingdevice, such as a computing tablet, a mobile phone or smart-phone, alaptop, a desktop, an Internet-of-Things (JOT) device, a server, awearable device, a set-top box, a wireless-enabled e-reader, or thelike. It will be understood that certain components are shown generally,and not all components of such a device are shown in device 2000.

In an example, the device 2000 comprises a SoC (System-on-Chip) 2001. Anexample boundary of the SOC 2001 is illustrated using dotted lines inFIG. 20 , with some example components being illustrated to be includedwithin SOC 2001—however, SOC 2001 may include any appropriate componentsof device 2000.

In some embodiments, device 2000 includes processor 2004. Processor 2110can include one or more physical devices, such as microprocessors,application processors, microcontrollers, programmable logic devices,processing cores, or other processing means. The processing operationsperformed by processor 2004 include the execution of an operatingplatform or operating system on which applications and/or devicefunctions are executed. The processing operations include operationsrelated to I/O (input/output) with a human user or with other devices,operations related to power management, operations related to connectingcomputing device 2000 to another device, and/or the like. The processingoperations may also include operations related to audio I/O and/ordisplay I/O.

In some embodiments, processor 2004 includes multiple processing cores(also referred to as cores) 2008 a, 2008 b, 2008 c. Although merelythree cores 2008 a, 2008 b, 2008 c are illustrated in FIG. 20 , theprocessor 2004 may include any other appropriate number of processingcores, e.g., tens, or even hundreds of processing cores. Processor cores2008 a, 2008 b, 2008 c may be implemented on a single integrated circuit(IC) chip. Moreover, the chip may include one or more shared and/orprivate caches, buses or interconnections, graphics and/or memorycontrollers, or other components.

In some embodiments, processor 2004 includes cache 2006. In an example,sections of cache 2006 may be dedicated to individual cores 2008 (e.g.,a first section of cache 2006 dedicated to core 2008 a, a second sectionof cache 2006 dedicated to core 2008 b, and so on). In an example, oneor more sections of cache 2006 may be shared among two or more of cores2008. Cache 2006 may be split in different levels, e.g., level 1 (L1)cache, level 2 (L2) cache, level 3 (L3) cache, etc.

In some embodiments, processor core 2004 may include a fetch unit tofetch instructions (including instructions with conditional branches)for execution by the core 2004. The instructions may be fetched from anystorage devices such as the memory 2030. Processor core 2004 may alsoinclude a decode unit to decode the fetched instruction. For example,the decode unit may decode the fetched instruction into a plurality ofmicro-operations. Processor core 2004 may include a schedule unit toperform various operations associated with storing decoded instructions.For example, the schedule unit may hold data from the decode unit untilthe instructions are ready for dispatch, e.g., until all source valuesof a decoded instruction become available. In one embodiment, theschedule unit may schedule and/or issue (or dispatch) decodedinstructions to an execution unit for execution.

The execution unit may execute the dispatched instructions after theyare decoded (e.g., by the decode unit) and dispatched (e.g., by theschedule unit). In an embodiment, the execution unit may include morethan one execution unit (such as an imaging computational unit, agraphics computational unit, a general-purpose computational unit,etc.). The execution unit may also perform various arithmetic operationssuch as addition, subtraction, multiplication, and/or division, and mayinclude one or more an arithmetic logic units (ALUs). In an embodiment,a co-processor (not shown) may perform various arithmetic operations inconjunction with the execution unit.

Further, an execution unit may execute instructions out-of-order. Hence,processor core 2004 may be an out-of-order processor core in oneembodiment. Processor core 2004 may also include a retirement unit. Theretirement unit may retire executed instructions after they arecommitted. In an embodiment, retirement of the executed instructions mayresult in processor state being committed from the execution of theinstructions, physical registers used by the instructions beingde-allocated, etc. The processor core 2004 may also include a bus unitto enable communication between components of the processor core 2004and other components via one or more buses. Processor core 2004 may alsoinclude one or more registers to store data accessed by variouscomponents of the core 2004 (such as values related to assigned apppriorities and/or sub-system states (modes) association.

In some embodiments, device 2000 comprises connectivity circuitries2031. For example, connectivity circuitries 2031 includes hardwaredevices (e.g., wireless and/or wired connectors and communicationhardware) and/or software components (e.g., drivers, protocol stacks),e.g., to enable device 2000 to communicate with external devices. Device2000 may be separate from the external devices, such as other computingdevices, wireless access points or base stations, etc.

In an example, connectivity circuitries 2031 may include multipledifferent types of connectivity. To generalize, the connectivitycircuitries 2031 may include cellular connectivity circuitries, wirelessconnectivity circuitries, etc. Cellular connectivity circuitries ofconnectivity circuitries 2031 refers generally to cellular networkconnectivity provided by wireless carriers, such as provided via GSM(global system for mobile communications) or variations or derivatives,CDMA (code division multiple access) or variations or derivatives, TDM(time division multiplexing) or variations or derivatives, 3rdGeneration Partnership Project (3GPP) Universal MobileTelecommunications Systems (UMTS) system or variations or derivatives,3GPP Long-Term Evolution (LTE) system or variations or derivatives, 3GPPLTE-Advanced (LTE-A) system or variations or derivatives, FifthGeneration (5G) wireless system or variations or derivatives, 5G mobilenetworks system or variations or derivatives, 5G New Radio (NR) systemor variations or derivatives, or other cellular service standards.Wireless connectivity circuitries (or wireless interface) of theconnectivity circuitries 2031 refers to wireless connectivity that isnot cellular, and can include personal area networks (such as Bluetooth,Near Field, etc.), local area networks (such as Wi-Fi), and/or wide areanetworks (such as WiMax), and/or other wireless communication. In anexample, connectivity circuitries 2031 may include a network interface,such as a wired or wireless interface, e.g., so that a system embodimentmay be incorporated into a wireless device, for example, cell phone orpersonal digital assistant.

In some embodiments, device 2000 comprises control hub 2032, whichrepresents hardware devices and/or software components related tointeraction with one or more I/O devices. For example, processor 2004may communicate with one or more of display 2022, one or more peripheraldevices 2024, storage devices 2028, one or more other external devices2029, etc., via control hub 2032. Control hub 2032 may be a chipset, aPlatform Control Hub (PCH), and/or the like.

For example, control hub 2032 illustrates one or more connection pointsfor additional devices that connect to device 2000, e.g., through whicha user might interact with the system. For example, devices (e.g.,devices 2029) that can be attached to device 2000 include microphonedevices, speaker or stereo systems, audio devices, video systems orother display devices, keyboard or keypad devices, or other I/O devicesfor use with specific applications such as card readers or otherdevices.

As mentioned above, control hub 2032 can interact with audio devices,display 2022, etc. For example, input through a microphone or otheraudio device can provide input or commands for one or more applicationsor functions of device 2000. Additionally, audio output can be providedinstead of, or in addition to display output. In another example, ifdisplay 2022 includes a touch screen, display 2022 also acts as an inputdevice, which can be at least partially managed by control hub 2032.There can also be additional buttons or switches on computing device2000 to provide I/O functions managed by control hub 2032. In oneembodiment, control hub 2032 manages devices such as accelerometers,cameras, light sensors or other environmental sensors, or other hardwarethat can be included in device 2000. The input can be part of directuser interaction, as well as providing environmental input to the systemto influence its operations (such as filtering for noise, adjustingdisplays for brightness detection, applying a flash for a camera, orother features).

In some embodiments, control hub 2032 may couple to various devicesusing any appropriate communication protocol, e.g., PCIe (PeripheralComponent Interconnect Express), USB (Universal Serial Bus),Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

In some embodiments, display 2022 represents hardware (e.g., displaydevices) and software (e.g., drivers) components that provide a visualand/or tactile display for a user to interact with device 2000. Display2022 may include a display interface, a display screen, and/or hardwaredevice used to provide a display to a user. In some embodiments, display2022 includes a touch screen (or touch pad) device that provides bothoutput and input to a user. In an example, display 2022 may communicatedirectly with the processor 2004. Display 2022 can be one or more of aninternal display device, as in a mobile electronic device or a laptopdevice or an external display device attached via a display interface(e.g., DisplayPort, etc.). In one embodiment display 2022 can be a headmounted display (HMD) such as a stereoscopic display device for use invirtual reality (VR) applications or augmented reality (AR)applications.

In some embodiments and although not illustrated in the figure, inaddition to (or instead of) processor 2004, device 2000 may includeGraphics Processing Unit (GPU) comprising one or more graphicsprocessing cores, which may control one or more aspects of displayingcontents on display 2022.

Control hub 2032 (or platform controller hub) may include hardwareinterfaces and connectors, as well as software components (e.g.,drivers, protocol stacks) to make peripheral connections, e.g., toperipheral devices 2024.

It will be understood that device 2000 could both be a peripheral deviceto other computing devices, as well as have peripheral devices connectedto it. Device 2000 may have a “docking” connector to connect to othercomputing devices for purposes such as managing (e.g., downloadingand/or uploading, changing, synchronizing) content on device 2000.Additionally, a docking connector can allow device 2000 to connect tocertain peripherals that allow computing device 2000 to control contentoutput, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, device 2000 can make peripheral connections viacommon or standards-based connectors. Common types can include aUniversal Serial Bus (USB) connector (which can include any of a numberof different hardware interfaces), DisplayPort including MiniDisplayPort(MDP), High Definition Multimedia Interface (HDMI), Firewire, or othertypes.

In some embodiments, connectivity circuitries 2031 may be coupled tocontrol hub 2032, e.g., in addition to, or instead of, being coupleddirectly to the processor 2004. In some embodiments, display 2022 may becoupled to control hub 2032, e.g., in addition to, or instead of, beingcoupled directly to processor 2004.

In some embodiments, device 2000 comprises memory 2030 coupled toprocessor 2004 via memory interface 2034. Memory 2030 includes memorydevices for storing information in device 2000. Memory can includenonvolatile (state does not change if power to the memory device isinterrupted) and/or volatile (state is indeterminate if power to thememory device is interrupted) memory devices. Memory device 2030 can bea dynamic random access memory (DRAM) device, a static random accessmemory (SRAM) device, flash memory device, phase-change memory device,or some other memory device having suitable performance to serve asprocess memory. In one embodiment, memory 2030 can operate as systemmemory for device 2000, to store data and instructions for use when theone or more processors 2004 executes an application or process. Memory2030 can store application data, user data, music, photos, documents, orother data, as well as system data (whether long-term or temporary)related to the execution of the applications and functions of device2000.

Elements of various embodiments and examples are also provided as amachine-readable medium (e.g., memory 2030) for storing thecomputer-executable instructions (e.g., instructions to implement anyother processes discussed herein). The machine-readable medium (e.g.,memory 2030) may include, but is not limited to, flash memory, opticaldisks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or opticalcards, phase change memory (PCM), or other types of machine-readablemedia suitable for storing electronic or computer-executableinstructions. For example, embodiments of the disclosure may bedownloaded as a computer program (e.g., BIOS) which may be transferredfrom a remote computer (e.g., a server) to a requesting computer (e.g.,a client) by way of data signals via a communication link (e.g., a modemor network connection).

In some embodiments, device 2000 comprises temperature measurementcircuitries 2040, e.g., for measuring temperature of various componentsof device 2000. In an example, temperature measurement circuitries 2040may be embedded, or coupled or attached to various components, whosetemperature are to be measured and monitored. For example, temperaturemeasurement circuitries 2040 may measure temperature of (or within) oneor more of cores 2008 a, 2008 b, 2008 c, voltage regulator 2014, memory2030, a mother-board of SOC 2001, and/or any appropriate component ofdevice 2000.

In some embodiments, device 2000 comprises power measurement circuitries2042, e.g., for measuring power consumed by one or more components ofthe device 2000. In an example, in addition to, or instead of, measuringpower, the power measurement circuitries 2042 may measure voltage and/orcurrent. In an example, the power measurement circuitries 2042 may beembedded, or coupled or attached to various components, whose power,voltage, and/or current consumption are to be measured and monitored.For example, power measurement circuitries 2042 may measure power,current and/or voltage supplied by one or more voltage regulators 2014,power supplied to SOC 2001, power supplied to device 2000, powerconsumed by processor 2004 (or any other component) of device 2000, etc.

In some embodiments, device 2000 comprises one or more voltage regulatorcircuitries, generally referred to as voltage regulator (VR) 2014. VR2014 generates signals at appropriate voltage levels, which may besupplied to operate any appropriate components of the device 2000.Merely as an example, VR 2014 is illustrated to be supplying signals toprocessor 2004 of device 2000. In some embodiments, VR 2014 receives oneor more Voltage Identification (VID) signals, and generates the voltagesignal at an appropriate level, based on the VID signals. Various typeof VRs may be utilized for the VR 2014. For example, VR 2014 may includea “buck” VR, “boost” VR, a combination of buck and boost VRs, lowdropout (LDO) regulators, switching DC-DC regulators, etc. Buck VR isgenerally used in power delivery applications in which an input voltageneeds to be transformed to an output voltage in a ratio that is smallerthan unity. Boost VR is generally used in power delivery applications inwhich an input voltage needs to be transformed to an output voltage in aratio that is larger than unity. In some embodiments, each processorcore has its own VR which is controlled by PCU 2010 a/b and/or PMIC2012. In some embodiments, each core has a network of distributed LDOsto provide efficient control for power management. The LDOs can bedigital, analog, or a combination of digital or analog LDOs.

In some embodiments, device 2000 comprises one or more clock generatorcircuitries, generally referred to as clock generator 2016. Clockgenerator 2016 generates clock signals at appropriate frequency levels,which may be supplied to any appropriate components of device 2000.Merely as an example, clock generator 2016 is illustrated to besupplying clock signals to processor 2004 of device 2000. In someembodiments, clock generator 2016 receives one or more FrequencyIdentification (FID) signals, and generates the clock signals at anappropriate frequency, based on the FID signals.

In some embodiments, device 2000 comprises battery 2018 supplying powerto various components of device 2000. Merely as an example, battery 2018is illustrated to be supplying power to processor 2004. Although notillustrated in the figures, device 2000 may comprise a chargingcircuitry, e.g., to recharge the battery, based on Alternating Current(AC) power supply received from an AC adapter.

In some embodiments, device 2000 comprises Power Control Unit (PCU) 2010(also referred to as Power Management Unit (PMU), Power Controller,etc.). In an example, some sections of PCU 2010 may be implemented byone or more processing cores 2008, and these sections of PCU 2010 aresymbolically illustrated using a dotted box and labelled PCU 2010 a. Inan example, some other sections of PCU 2010 may be implemented outsidethe processing cores 2008, and these sections of PCU 2010 aresymbolically illustrated using a dotted box and labelled as PCU 2010 b.PCU 2010 may implement various power management operations for device2000. PCU 2010 may include hardware interfaces, hardware circuitries,connectors, registers, etc., as well as software components (e.g.,drivers, protocol stacks), to implement various power managementoperations for device 2000.

In some embodiments, device 2000 comprises Power Management IntegratedCircuit (PMIC) 2012, e.g., to implement various power managementoperations for device 2000. In some embodiments, PMIC 2012 is aReconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel®Mobile Voltage Positioning). In an example, the PMIC is within an ICchip separate from processor 2004. The may implement various powermanagement operations for device 2000. PMIC 2012 may include hardwareinterfaces, hardware circuitries, connectors, registers, etc., as wellas software components (e.g., drivers, protocol stacks), to implementvarious power management operations for device 2000.

In an example, device 2000 comprises one or both PCU 2010 or PMIC 2012.In an example, any one of PCU 2010 or PMIC 2012 may be absent in device2000, and hence, these components are illustrated using dotted lines.

Various power management operations of device 2000 may be performed byPCU 2010, by PMIC 2012, or by a combination of PCU 2010 and PMIC 2012.For example, PCU 2010 and/or PMIC 2012 may select a power state (e.g.,P-state) for various components of device 2000. For example, PCU 2010and/or PMIC 2012 may select a power state (e.g., in accordance with theACPI (Advanced Configuration and Power Interface) specification) forvarious components of device 2000. Merely as an example, PCU 2010 and/orPMIC 2012 may cause various components of the device 2000 to transitionto a sleep state, to an active state, to an appropriate C state (e.g.,C0 state, or another appropriate C state, in accordance with the ACPIspecification), etc. In an example, PCU 2010 and/or PMIC 2012 maycontrol a voltage output by VR 2014 and/or a frequency of a clock signaloutput by the clock generator, e.g., by outputting the VID signal and/orthe FID signal, respectively. In an example, PCU 2010 and/or PMIC 2012may control battery power usage, charging of battery 2018, and featuresrelated to power saving operation.

The clock generator 2016 can comprise a phase locked loop (PLL),frequency locked loop (FLL), or any suitable clock source. In someembodiments, each core of processor 2004 has its own clock source. Assuch, each core can operate at a frequency independent of the frequencyof operation of the other core. In some embodiments, PCU 2010 and/orPMIC 2012 performs adaptive or dynamic frequency scaling or adjustment.For example, clock frequency of a processor core can be increased if thecore is not operating at its maximum power consumption threshold orlimit. In some embodiments, PCU 2010 and/or PMIC 2012 determines theoperating condition of each core of a processor, and opportunisticallyadjusts frequency and/or power supply voltage of that core without thecore clocking source (e.g., PLL of that core) losing lock when the PCU2010 and/or PMIC 2012 determines that the core is operating below atarget performance level. For example, if a core is drawing current froma power supply rail less than a total current allocated for that core orprocessor 2004, then PCU 2010 and/or PMIC 2012 can temporarily increasethe power draw for that core or processor 2004 (e.g., by increasingclock frequency and/or power supply voltage level) so that the core orprocessor 2004 can perform at a higher performance level. As such,voltage and/or frequency can be increased temporality for processor 2004without violating product reliability.

In an example, PCU 2010 and/or PMIC 2012 may perform power managementoperations, e.g., based at least in part on receiving measurements frompower measurement circuitries 2042, temperature measurement circuitries2040, charge level of battery 2018, and/or any other appropriateinformation that may be used for power management. To that end, PMIC2012 is communicatively coupled to one or more sensors to sense/detectvarious values/variations in one or more factors having an effect onpower/thermal behavior of the system/platform. Examples of the one ormore factors include electrical current, voltage droop, temperature,operating frequency, operating voltage, power consumption, inter-corecommunication activity, etc. One or more of these sensors may beprovided in physical proximity (and/or thermal contact/coupling) withone or more components or logic/IP blocks of a computing system.Additionally, sensor(s) may be directly coupled to PCU 2010 and/or PMIC2012 in at least one embodiment to allow PCU 2010 and/or PMIC 2012 tomanage processor core energy at least in part based on value(s) detectedby one or more of the sensors.

Also illustrated is an example software stack of device 2000 (althoughnot all elements of the software stack are illustrated). Merely as anexample, processors 2004 may execute application programs 2050,Operating System 2052, one or more Power Management (PM) specificapplication programs (e.g., generically referred to as PM applications2058), and/or the like. PM applications 2058 may also be executed by thePCU 2010 and/or PMIC 2012. OS 2052 may also include one or more PMapplications 2056 a, 2056 b, 2056 c. The OS 2052 may also includevarious drivers 2054 a, 2054 b, 2054 c, etc., some of which may bespecific for power management purposes. In some embodiments, device 2000may further comprise a Basic Input/Output System (BIOS) 2020. BIOS 2020may communicate with OS 2052 (e.g., via one or more drivers 2054),communicate with processors 2004, etc.

For example, one or more of PM applications 2058, 2056, drivers 2054,BIOS 2020, etc. may be used to implement power management specifictasks, e.g., to control voltage and/or frequency of various componentsof device 2000, to control wake-up state, sleep state, and/or any otherappropriate power state of various components of device 2000, controlbattery power usage, charging of the battery 2018, features related topower saving operation, etc.

Some embodiments variously facilitate a change to a frequency of aconnectivity fabric (e.g., the fabric comprising connectivitycircuitries 2031 and/or other interconnect circuitry of computing device2000), where the change is transparent to processor 2004 and one or moreother devices that are coupled thereto. Additionally or alternatively,some embodiments variously enable processor 2004 operable to configure amode of an external voltage regulator (not shown) which delivers powerto processor 2004—e.g., wherein the mode is to mitigate a draw ofcurrent from the voltage regulator. Additionally or alternatively, someembodiments variously enable processor 2004 to log a time (prior to anactivation of some processor circuitry) when an indication of a powerstate transition is detected, where a latency of a power statetransition is subsequently determined and reported to a software processbased on the logged time.

Additionally or alternatively, some embodiments variously provide powermanagement circuits (of the power management circuitries 2042, forexample) at different respective IC chips, where the provide powermanagement circuits are coupled to negotiate a distribution of powerbetween the IC chips. Additionally or alternatively, some embodimentsvariously provide circuitry (of the power management circuitries 2042,for example), which is external to processor 2004, is operable to detecta thermal condition of processor 2004 and, based on such monitoring, tochange a delivery of power to processor 2004 while it remains in a sleep(or other low power) state.

Additionally or alternatively, some embodiments variously enable stateof processor 2004 to be stored based on a prediction as to whether aSRAM (or other memory) internal to processor 2004, or some externalresource such as memory 2030, is likely to be a more power efficientrepository of such state. Additionally or alternatively, someembodiments variously enable processor 2004 to generate control signalsbased on values which each indicate a different respective latency of acorresponding power gate (not shown) that is coupled to processor 2004.The control signals are communicated each to a different respective loadcircuit of processor 2004, wherein the load circuits initiate respectiveoperations of a power state transition at different times based on thecontrol signals.

In the description herein, numerous details are discussed to provide amore thorough explanation of the embodiments of the present disclosure.It will be apparent to one skilled in the art, however, that embodimentsof the present disclosure may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, in order to avoidobscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals arerepresented with lines. Some lines may be thicker, to indicate a greaternumber of constituent signal paths, and/or have arrows at one or moreends, to indicate a direction of information flow. Such indications arenot intended to be limiting. Rather, the lines are used in connectionwith one or more exemplary embodiments to facilitate easierunderstanding of a circuit or a logical unit. Any represented signal, asdictated by design needs or preferences, may actually comprise one ormore signals that may travel in either direction and may be implementedwith any suitable type of signal scheme.

Throughout the specification, and in the claims, the term “connected”means a direct connection, such as electrical, mechanical, or magneticconnection between the things that are connected, without anyintermediary devices. The term “coupled” means a direct or indirectconnection, such as a direct electrical, mechanical, or magneticconnection between the things that are connected or an indirectconnection, through one or more passive or active intermediary devices.The term “circuit” or “module” may refer to one or more passive and/oractive components that are arranged to cooperate with one another toprovide a desired function. The term “signal” may refer to at least onecurrent signal, voltage signal, magnetic signal, or data/clock signal.The meaning of “a,” “an,” and “the” include plural references. Themeaning of “in” includes “in” and “on.”

The term “device” may generally refer to an apparatus according to thecontext of the usage of that term. For example, a device may refer to astack of layers or structures, a single structure or layer, a connectionof various structures having active and/or passive elements, etc.Generally, a device is a three-dimensional structure with a plane alongthe x-y direction and a height along the z direction of an x-y-zCartesian coordinate system. The plane of the device may also be theplane of an apparatus which comprises the device.

The term “scaling” generally refers to converting a design (schematicand layout) from one process technology to another process technologyand subsequently being reduced in layout area. The term “scaling”generally also refers to downsizing layout and devices within the sametechnology node. The term “scaling” may also refer to adjusting (e.g.,slowing down or speeding up—i.e. scaling down, or scaling uprespectively) of a signal frequency relative to another parameter, forexample, power supply level.

The terms “substantially,” “close,” “approximately,” “near,” and“about,” generally refer to being within +/−10% of a target value. Forexample, unless otherwise specified in the explicit context of theiruse, the terms “substantially equal,” “about equal” and “approximatelyequal” mean that there is no more than incidental variation betweenamong things so described. In the art, such variation is typically nomore than +/−10% of a predetermined target value.

It is to be understood that the terms so used are interchangeable underappropriate circumstances such that the embodiments of the inventiondescribed herein are, for example, capable of operation in otherorientations than those illustrated or otherwise described herein.

Unless otherwise specified the use of the ordinal adjectives “first,”“second,” and “third,” etc., to describe a common object, merelyindicate that different instances of like objects are being referred toand are not intended to imply that the objects so described must be in agiven sequence, either temporally, spatially, in ranking or in any othermanner.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,”“under,” and the like in the description and in the claims, if any, areused for descriptive purposes and not necessarily for describingpermanent relative positions. For example, the terms “over,” “under,”“front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” asused herein refer to a relative position of one component, structure, ormaterial with respect to other referenced components, structures ormaterials within a device, where such physical relationships arenoteworthy. These terms are employed herein for descriptive purposesonly and predominantly within the context of a device z-axis andtherefore may be relative to an orientation of a device. Hence, a firstmaterial “over” a second material in the context of a figure providedherein may also be “under” the second material if the device is orientedupside-down relative to the context of the figure provided. In thecontext of materials, one material disposed over or under another may bedirectly in contact or may have one or more intervening materials.Moreover, one material disposed between two materials may be directly incontact with the two layers or may have one or more intervening layers.In contrast, a first material “on” a second material is in directcontact with that second material. Similar distinctions are to be madein the context of component assemblies.

The term “between” may be employed in the context of the z-axis, x-axisor y-axis of a device. A material that is between two other materialsmay be in contact with one or both of those materials, or it may beseparated from both of the other two materials by one or moreintervening materials. A material “between” two other materials maytherefore be in contact with either of the other two materials, or itmay be coupled to the other two materials through an interveningmaterial. A device that is between two other devices may be directlyconnected to one or both of those devices, or it may be separated fromboth of the other two devices by one or more intervening devices.

As used throughout this description, and in the claims, a list of itemsjoined by the term “at least one of” or “one or more of” can mean anycombination of the listed terms. For example, the phrase “at least oneof A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B andC. It is pointed out that those elements of a figure having the samereference numbers (or names) as the elements of any other figure canoperate or function in any manner similar to that described, but are notlimited to such.

In addition, the various elements of combinatorial logic and sequentiallogic discussed in the present disclosure may pertain both to physicalstructures (such as AND gates, OR gates, or XOR gates), or tosynthesized or otherwise optimized collections of devices implementingthe logical structures that are Boolean equivalents of the logic underdiscussion.

Techniques and architectures for managing power delivery and/orconsumption by a processor are described herein. In the abovedescription, for purposes of explanation, numerous specific details areset forth in order to provide a thorough understanding of certainembodiments. It will be apparent, however, to one skilled in the artthat certain embodiments can be practiced without these specificdetails. In other instances, structures and devices are shown in blockdiagram form in order to avoid obscuring the description.

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the invention. The appearances of the phrase “in one embodiment” invarious places in the specification are not necessarily all referring tothe same embodiment.

Some portions of the detailed description herein are presented in termsof algorithms and symbolic representations of operations on data bitswithin a computer memory. These algorithmic descriptions andrepresentations are the means used by those skilled in the computingarts to most effectively convey the substance of their work to othersskilled in the art. An algorithm is here, and generally, conceived to bea self-consistent sequence of steps leading to a desired result. Thesteps are those requiring physical manipulations of physical quantities.Usually, though not necessarily, these quantities take the form ofelectrical or magnetic signals capable of being stored, transferred,combined, compared, and otherwise manipulated. It has proven convenientat times, principally for reasons of common usage, to refer to thesesignals as bits, values, elements, symbols, characters, terms, numbers,or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the discussion herein, itis appreciated that throughout the description, discussions utilizingterms such as “processing” or “computing” or “calculating” or“determining” or “displaying” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical(electronic) quantities within the computer system's registers andmemories into other data similarly represented as physical quantitieswithin the computer system memories or registers or other suchinformation storage, transmission or display devices.

Certain embodiments also relate to apparatus for performing theoperations herein. This apparatus may be specially constructed for therequired purposes, or it may comprise a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program may be stored in a computerreadable storage medium, such as, but is not limited to, any type ofdisk including floppy disks, optical disks, CD-ROMs, andmagnetic-optical disks, read-only memories (ROMs), random accessmemories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic oroptical cards, or any type of media suitable for storing electronicinstructions, and coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general purposesystems may be used with programs in accordance with the teachingsherein, or it may prove convenient to construct more specializedapparatus to perform the required method steps. The required structurefor a variety of these systems will appear from the description herein.In addition, certain embodiments are not described with reference to anyparticular programming language. It will be appreciated that a varietyof programming languages may be used to implement the teachings of suchembodiments as described herein.

In one or more first embodiments, a device comprises an interconnectfabric comprising one or more nodes, an end point device coupled to theinterconnect fabric via an asynchronous device, a clock controllercoupled to provide a clock signal to the one or more nodes, wherein,based on the clock signal, the one or more nodes are to communicate withthe end point device via the asynchronous device while a first clockdomain comprises the one or more nodes, and while a second clock domaincomprises the end point device. The device further comprises a powermanagement (PM) controller to communicate a control signal to the clockcontroller while the clock signal is cycled at a first frequency,wherein the control signal indicates that the first clock domain is tobe transitioned from the first frequency to a second frequency, wherein,in response to the control signal, the clock controller is to stall theclock signal throughout a period of time which is equal to or greaterthan a duration of three cycles of a lower one of the first frequency orthe second frequency, and after the period of time, to cycle the clocksignal at the second frequency.

In one or more second embodiments, further to the first embodiment, theend point device is to be able to communicate with the asynchronousdevice throughout the period of time.

In one or more third embodiments, further to the first embodiment or thesecond embodiment, the period of time is equal to or less than aduration of five cycles of the lower one of the first frequency or thesecond frequency.

In one or more fourth embodiments, further to any of the first throughthird embodiments, the asynchronous device comprises an asynchronousbuffered port.

In one or more fifth embodiments, further to any of the first throughfourth embodiments, the clock controller further comprises a register tostore a value representing the period of time, wherein the clock signalis to stall the clock signal based on the value.

In one or more sixth embodiments, further to any of the first throughfifth embodiments, the control signal is a first control signal totrigger a frequency of the first clock domain, and wherein the PMcontroller is further to communicate a second control signal to theclock controller prior to the first control signal, wherein the secondcontrol signal comprises an identifier of the second frequency.

In one or more seventh embodiments, further to any of the first throughsixth embodiments, the interconnect fabric, the one or more nodes, theclock signal, and the control signal are, respectively, a firstinterconnect fabric, a first one or more nodes, a first clock signal,and a first control signal, wherein the device further comprises asecond interconnect fabric comprising a second one or more nodes coupledto the first interconnect fabric, wherein the end point device iscoupled to the first interconnect fabric via the second interconnectfabric. The clock controller is further coupled to provide a secondclock signal to the second one or more nodes, wherein, based on thesecond clock signal, the second one or more nodes are to communicatewith the first one or more nodes while a third clock domain comprisesthe second one or more nodes, wherein the PM controller is further tocommunicate a second control signal to the clock controller while thesecond clock signal is cycled at a third frequency, wherein the secondcontrol signal indicates that the third clock domain is to betransitioned from the third frequency to a fourth frequency. In responseto the second control signal, the clock controller is to stall thesecond clock signal throughout a second period of time while the firstclock signal is to continue to cycle at one of the first frequency orthe second frequency, wherein the second period of time is equal to orgreater than a duration of three cycles of a lower one of the thirdfrequency or the fourth frequency, and after the second period of time,to cycle the second clock signal at the fourth frequency.

In one or more eighth embodiments, further to any of the first throughseventh embodiments, the end point device comprises a processor.

In one or more ninth embodiments, a device comprises a processor, afabric comprising an asynchronous port and nodes coupled to provideswitched communication, based on a clock signal, with the processor viathe asynchronous port, and a clock controller coupled the fabric, theclock controller to provide the clock signal to the nodes, receive acontrol signal while a first clock domain comprises the nodes, and whilea second clock domain comprises the processor, and transition the firstclock domain from a first frequency to a second frequency based on thecontrol signal, wherein the clock controller is to stall the clocksignal throughout a period of time which is equal to or greater than aduration of three cycles of a lower one of the first frequency or thesecond frequency, and cycle the clock signal at the second frequencyafter the period of time.

In one or more tenth embodiments, further to the ninth embodiment, theperiod of time is equal to or less than a duration of five cycles of thelower one of the first frequency or the second frequency.

In one or more eleventh embodiments, further to the ninth embodiment orthe tenth embodiment, the clock controller further comprises a registerto store a value representing the period of time, wherein the clocksignal is to stall the clock signal based on the value.

In one or more twelfth embodiments, further to any of the ninth througheleventh embodiments, the control signal is a first control signal totrigger a frequency of the first clock domain, and wherein the clockcontroller is further to receive a second control signal prior to thefirst control signal, wherein the second control signal comprises anidentifier of the second frequency.

In one or more thirteenth embodiments, further to any of the ninththrough twelfth embodiments, the fabric, the nodes, the clock signal,and the control signal are, respectively, a first fabric, first nodes, afirst clock signal, and a first control signal, wherein the devicefurther comprises a second fabric comprising second nodes coupled to thefirst fabric, wherein the processor is coupled to the first fabric viathe second fabric, wherein the clock controller is further coupled toprovide a second clock signal to the second nodes, wherein, based on thesecond clock signal, the second nodes are to communicate with the firstnodes while a third clock domain comprises the second nodes, wherein theclock controller is further to receive a second control signal while thesecond clock signal is cycled at a third frequency. In response to thesecond control signal, the clock controller is to stall the second clocksignal throughout a second period of time while the first clock signalis to continue to cycle at one of the first frequency or the secondfrequency, wherein the second period of time is equal to or greater thana duration of three cycles of a lower one of the third frequency or thefourth frequency, and after the second period of time, to cycle thesecond clock signal at the fourth frequency.

In one or more fourteenth embodiments, a system comprises one or moreintegrated circuit (IC) chips comprising an interconnect fabriccomprising one or more nodes, an end point device coupled to theinterconnect fabric via an asynchronous device, a clock controllercoupled to provide a clock signal to the one or more nodes, wherein,based on the clock signal, the one or more nodes are to communicate withthe end point device via the asynchronous device while a first clockdomain comprises the one or more nodes, and while a second clock domaincomprises the end point device, and a power management (PM) controllerto communicate a control signal to the clock controller while the clocksignal is cycled at a first frequency, wherein the control signalindicates that the first clock domain is to be transitioned from thefirst frequency to a second frequency. In response to the controlsignal, the clock controller is to stall the clock signal throughout aperiod of time which is equal to or greater than a duration of threecycles of a lower one of the first frequency or the second frequency,and after the period of time, to cycle the clock signal at the secondfrequency. The system further comprises a display device coupled to theone or more IC chips, the display device to display an image based on asignal communicated with the one or more IC chips.

In one or more fifteenth embodiments, further to the fourteenthembodiment, the end point device is to be able to communicate with theasynchronous device throughout the period of time.

In one or more sixteenth embodiments, further to the fourteenthembodiment or the fifteenth embodiment, the period of time is equal toor less than a duration of five cycles of the lower one of the firstfrequency or the second frequency.

In one or more seventeenth embodiments, further to any of the fourteenththrough sixteenth embodiments, the asynchronous device comprises anasynchronous buffered port.

In one or more eighteenth embodiments, further to any of the fourteenththrough seventeenth embodiments, the clock controller further comprisesa register to store a value representing the period of time, wherein theclock signal is to stall the clock signal based on the value.

In one or more nineteenth embodiments, further to any of the fourteenththrough eighteenth embodiments, the control signal is a first controlsignal to trigger a frequency of the first clock domain, and wherein thePM controller is further to communicate a second control signal to theclock controller prior to the first control signal, wherein the secondcontrol signal comprises an identifier of the second frequency.

In one or more twentieth embodiments, further to any of the fourteenththrough nineteenth embodiments, wherein the interconnect fabric, the oneor more nodes, the clock signal, and the control signal are,respectively, a first interconnect fabric, a first one or more nodes, afirst clock signal, and a first control signal, wherein the one or moreIC chips further comprises a second interconnect fabric comprising asecond one or more nodes coupled to the first interconnect fabric,wherein the end point device is coupled to the first interconnect fabricvia the second interconnect fabric, wherein the clock controller isfurther coupled to provide a second clock signal to the second one ormore nodes, wherein, based on the second clock signal, the second one ormore nodes are to communicate with the first one or more nodes while athird clock domain comprises the second one or more nodes, wherein thePM controller is further to communicate a second control signal to theclock controller while the second clock signal is cycled at a thirdfrequency, wherein the second control signal indicates that the thirdclock domain is to be transitioned from the third frequency to a fourthfrequency. In response to the second control signal, the clockcontroller is to stall the second clock signal throughout a secondperiod of time while the first clock signal is to continue to cycle atone of the first frequency or the second frequency, wherein the secondperiod of time is equal to or greater than a duration of three cycles ofa lower one of the third frequency or the fourth frequency, and afterthe second period of time, cycle the second clock signal at the fourthfrequency.

In one or more twenty-first embodiments, further to any of thefourteenth through twentieth embodiments, the end point device comprisesa processor.

In one or more twenty-second embodiments, a method comprises, with acontroller circuit, providing a clock signal to one or more nodes of aninterconnect fabric, with the one or more nodes, communicating with anend point device based on the clock signal, wherein the end point deviceis coupled to the interconnect fabric via an asynchronous device, thecommunicating while a first clock domain comprises the one or morenodes, and while a second clock domain comprises the end point device,while the clock signal is cycling at a first frequency, detecting at thecontroller circuit that the first clock domain is to be transitionedfrom the first frequency to a second frequency. The method furthercomprises, based on the detecting, stalling the clock signal throughouta period of time which is equal to or greater than a duration of threecycles of a lower one of the first frequency or the second frequency,and after the period of time, cycling the clock signal at the secondfrequency.

In one or more twenty-third embodiments, further to the twenty-secondembodiment, the method further comprises with the end point device,communicating with the asynchronous device during the period of time.

In one or more twenty-fourth embodiments, further to the twenty-secondembodiment or the twenty-third embodiment, the period of time is equalto or less than a duration of five cycles of the lower one of the firstfrequency or the second frequency.

In one or more twenty-fifth embodiments, further to any of thetwenty-second through twenty-fourth embodiments, the asynchronous devicecomprises an asynchronous buffered port.

In one or more twenty-sixth embodiments, further to any of thetwenty-second through twenty-fifth embodiments, the method furthercomprises storing, at a register of the the clock controller, a valuerepresenting the period of time, wherein the clock signal stalls theclock signal based on the value.

In one or more twenty-seventh embodiments, further to any of thetwenty-second through twenty-sixth embodiments, the method furthercomprises communicating a first signal, from a power manager circuit tothe controller circuit, the first signal comprising an identifier of thesecond frequency, and after communicating the first signal,communicating a second signal, from a power manager circuit to thecontroller circuit, to trigger the stalling.

In one or more twenty-eighth embodiments, further to any of thetwenty-second through twenty-seventh embodiments, the interconnectfabric, the one or more nodes, the clock signal, and the control signalare, respectively, a first interconnect fabric, a first one or morenodes, a first clock signal, and a first control signal, the methodfurther comprises with the controller circuit, providing a second clocksignal to a second one or more nodes of a second interconnect fabriccoupled to the first interconnect fabric, wherein the end point deviceis coupled to the first interconnect fabric via the second interconnectfabric, while the second clock signal is cycling at a third frequency,performing a second detecting at the controller circuit that the secondclock domain is to be transitioned from the third frequency to a fourthfrequency. The method further comprises, based on the second detecting,stalling the second clock signal throughout a second period of timewhich is equal to or greater than a duration of three cycles of a lowerone of the third frequency or the fourth frequency, and after the secondperiod of time, cycling the second clock signal at the fourth frequency.

In one or more twenty-ninth embodiments, a processor comprises a firstvoltage regulator (VR), interface circuitry to couple the processor to asecond VR, wherein the first VR is to receive a second voltage from thesecond VR via the interface circuitry, and to generate a first voltagebased on the second voltage, and power management circuitry, coupled tothe interface circuitry, to receive an indication of a power deliverycondition of the processor, and based on the indication, accessreference information which indicates performance characteristics of thefirst VR and the second VR. The power management circuitry is further toperform an evaluation, based on the reference information, whichdetermines that a first mode of the first VR is compatible with athreshold maximum current of the second VR, wherein the first mode isselected over a second mode of the first VR based on the evaluation, andbased on the evaluation, signal the second VR to operate according to athird mode to deliver power to the first VR.

In one or more thirtieth embodiments, further to the twenty-ninthembodiment, power management circuitry is further to receive thereference information via the interface circuitry.

In one or more thirty-first embodiments, further to the thirtiethembodiment, the power management circuitry to receive the referenceinformation comprises the power management circuitry to receive updatedperformance characteristic information.

In one or more thirty-second embodiments, further to any of thetwenty-ninth through thirty-first embodiments, the power managementcircuitry to perform the evaluation comprises the power managementcircuitry to identify modes of the second VR which satisfy a thresholdminimum voltage requirement of the first VR, and perform a selection ofthe first mode from among the identified modes.

In one or more thirty-third embodiments, further to the thirty-secondembodiment, the identified modes each correspond to a differentrespective current level of a plurality of current levels, wherein theselection is based on a determination that a first current levelcorresponding to the first mode is a lowest one of the plurality ofcurrent levels.

In one or more thirty-fourth embodiments, further to any of thetwenty-ninth through thirty-third embodiments, the power managementcircuitry to receive the indication of the power delivery conditioncomprises the power management circuitry to identify a power state towhich the processor is to be transitioned.

In one or more thirty-fifth embodiments, further to any of thetwenty-ninth through thirty-fourth embodiments, the power managementcircuitry is to receive the indication during a power state of theprocessor, and wherein the processor is to maintain the power stateafter a transition of the second VR to the third mode.

In one or more thirty-sixth embodiments, one or more non-transitorycomputer-readable storage media having stored thereon instructionswhich, when executed by one or more processing units, cause the one ormore processing units to perform a method at a processor, wherein themethod comprises with a first voltage regulator (VR) of the processor,generating a first voltage based on a second voltage from a second VRwhich is coupled to the processor, receiving an indication of a powerdelivery condition of the processor, and based on the indication,accessing reference information which indicates performancecharacteristics of the first VR and the second VR. The method furthercomprises performing an evaluation, based on the reference information,which determines that a first mode of the first VR is compatible with athreshold maximum current of the second VR, wherein the first mode isselected over a second mode of the first VR based on the evaluation, andbased on the evaluation, signaling the second VR to operate according toa third mode to deliver power to the first VR.

In one or more thirty-seventh embodiments, further to the thirty-sixthembodiment, the method further comprises receiving the referenceinformation from an agent external to the processor.

In one or more thirty-eighth embodiments, further to the thirty-seventhembodiment, receiving the reference information comprises receivingupdated performance characteristic information.

In one or more thirty-ninth embodiments, further to any of thethirty-sixth through thirty-eighth embodiments, performing theevaluation comprises identifying modes of the second VR which satisfy athreshold minimum voltage requirement of the first VR, and performing aselection of the first mode from among the identified modes.

In one or more fortieth embodiments, further to the thirty-ninthembodiment, the identified modes each correspond to a differentrespective current level of a plurality of current levels, wherein theselection is based on a determination that a first current levelcorresponding to the first mode is a lowest one of the plurality ofcurrent levels.

In one or more forty-first embodiments, further to any of thethirty-sixth through fortieth embodiments, receiving the indication ofthe power delivery condition comprises identifying a power state towhich the processor is to be transitioned.

In one or more forty-second embodiments, further to any of thethirty-sixth through forty-first embodiments, the indication is receivedduring a power state of the processor, and wherein the processormaintains the power state after a transition of the second VR to thethird mode.

In one or more forty-third embodiments, a system comprises a firstvoltage regulator (VR), a processor coupled to receive a first voltagefrom the first VR, the processor comprising a second voltage regulator(VR) to generate a second voltage based on the first voltage, and powermanagement circuitry to receive an indication of a power deliverycondition of the processor, and based on the indication, accessreference information which indicates performance characteristics of thefirst VR and the second VR. The power management circuitry is further toperform an evaluation, based on the reference information, whichdetermines that a first mode of the second VR is compatible with athreshold maximum current of the first VR, wherein the first mode isselected over a second mode of the second VR based on the evaluation,and based on the evaluation, signal the first VR to operate according toa third mode to deliver power to the second VR. The system furthercomprises a display device coupled to the processor, the display deviceto display an image based on a signal communicated with the processor.

In one or more forty-fourth embodiments, further to the forty-thirdembodiment, the power management circuitry is further to receive thereference information via the interface circuitry.

In one or more forty-fifth embodiments, further to the forty-fourthembodiment, the power management circuitry to receive the referenceinformation comprises the power management circuitry to receive updatedperformance characteristic information.

In one or more forty-sixth embodiments, further to any of theforty-third through forty-fifth embodiments, the power managementcircuitry to perform the evaluation comprises the power managementcircuitry to identify modes of the first VR which satisfy a thresholdminimum voltage requirement of the first VR, and perform a selection ofthe first mode from among the identified modes.

In one or more forty-seventh embodiments, further to the forty-sixthembodiment, the identified modes each correspond to a differentrespective current level of a plurality of current levels, wherein theselection is based on a determination that a first current levelcorresponding to the first mode is a lowest one of the plurality ofcurrent levels.

In one or more forty-eighth embodiments, further to any of theforty-third through forty-seventh embodiments, the power managementcircuitry to receive the indication of the power delivery conditioncomprises the power management circuitry to identify a power state towhich the processor is to be transitioned.

In one or more forty-ninth embodiments, further to any of theforty-third through forty-eighth embodiments, the power managementcircuitry is to receive the indication during a power state of theprocessor, and wherein the processor is to maintain the power stateafter a transition of the first VR to the third mode.

In one or more fiftieth embodiments, a method at a processor compriseswith a first voltage regulator (VR) of the processor, generating a firstvoltage based on a second voltage from a second VR which is coupled tothe processor, receiving an indication of a power delivery condition ofthe processor, and based on the indication, accessing referenceinformation which indicates performance characteristics of the first VRand the second VR. The method further comprises performing anevaluation, based on the reference information, which determines that afirst mode of the first VR is compatible with a threshold maximumcurrent of the second VR, wherein the first mode is selected over asecond mode of the first VR based on the evaluation, and based on theevaluation, signaling the second VR to operate according to a third modeto deliver power to the first VR.

In one or more fifty-first embodiments, further to the fiftiethembodiment, the method further comprises receiving the referenceinformation from an agent external to the processor.

In one or more fifty-second embodiments, further to the fifty-firstembodiment, receiving the reference information comprises receivingupdated performance characteristic information.

In one or more fifty-third embodiments, further to any of the fiftieththrough fifty-second embodiments, performing the evaluation comprisesidentifying modes of the second VR which satisfy a threshold minimumvoltage requirement of the first VR, and performing a selection of thefirst mode from among the identified modes.

In one or more fifty-fourth embodiments, further to the fifty-thirdembodiment, the identified modes each correspond to a differentrespective current level of a plurality of current levels, wherein theselection is based on a determination that a first current levelcorresponding to the first mode is a lowest one of the plurality ofcurrent levels.

In one or more fifty-fifth embodiments, further to any of the fiftieththrough fifty-fourth embodiments, receiving the indication of the powerdelivery condition comprises identifying a power state to which theprocessor is to be transitioned.

In one or more fifty-sixth embodiments, further to any of the fiftieththrough fifty-fifth embodiments, the indication is received during apower state of the processor, and wherein the processor maintains thepower state after a transition of the second VR to the third mode.

In one or more fifty-seventh embodiments, a processor comprises firstcircuitry to detect a need to perform a power state transition with theprocessor, second circuitry coupled to receive from the first circuitrya signal which indicates the need, wherein based on the signal, thesecond circuitry is to log a time t0 of a communication of the signal,and to generate a control signal, and third circuitry, coupled to thesecond circuitry, to initiate a wake-up operation in response to thecontrol signal, request an indication of the time t0 from the secondcircuitry after the wake-up operation, and provide to an operatingsystem a communication comprising a value, based on the indication ofthe time t0, which identifies a latency of the power state transition.

In one or more fifty-eighth embodiments, further to the fifty-seventhembodiment, the third circuitry is further to perform one or moreoperations of the power state transition after a receipt of theindication of the time t0 from the second circuitry.

In one or more fifty-ninth embodiments, further to the fifty-seventhembodiment or the fifty-eighth embodiment, the third circuitry is tocompute a duration of the latency based on the indication of the timet0, wherein the latency comprises a first period of time from the timet0 to a transmission of the control signal from the second circuitry.

In one or more sixtieth embodiments, further to the fifty-ninthembodiment, the third circuitry to request the indication of the time t0comprises the third circuitry to send a query to the second circuitry,and wherein the latency further comprises a second period of time duringthe wake-up operation, and before a communication of the query.

In one or more sixty-first embodiments, further to the sixtiethembodiment, the latency further comprises a third period of time fromthe communication of the query to a communication of the indication ofthe time t0 to the third circuitry.

In one or more sixty-second embodiments, further to the sixty-firstembodiment, the latency further comprises a fourth period of time afterthe communication of the indication of the time t0 to the thirdcircuitry.

In one or more sixty-third embodiments, further to any of thefifty-seventh through sixty-second embodiments, the third circuitry isto send a query to the second circuitry to request the indication of thetime t0, and wherein the second circuitry, based on the query, is tocalculate a total time between the time t0 and a time of a communicationof the query.

In one or more sixty-fourth embodiments, further to any of thefifty-seventh through sixty-third embodiments, the power statetransition includes a transition of the processor from a first powerstate which disables an execution of software to a second power statewhich enables the execution of software.

In one or more sixty-fifth embodiments, a device comprises a processorcomprising a controller unit to receive a first signal comprising anindication of a need to perform a power state transition with theprocessor, and log a time t0 of a communication of the first signal. Theprocessor further comprises a power management unit coupled to receivefrom the controller unit a second signal based on the indication. Thepower management unit is further to perform a wake-up operation inresponse to the second signal, determine the time t0 from the controllerunit after the wake-up operation, and based on the time t0, to generatean output comprising an identifier of a latency of the power statetransition.

In one or more sixty-sixth embodiments, further to the sixty-fifthembodiment, the power management unit is further to perform one or moreoperations of the power state transition after a receipt of theindication of the time t0 from the controller unit.

In one or more sixty-seventh embodiments, further to the sixty-fifthembodiment or the sixty-sixth embodiment, the power management unit isto compute a duration of the latency based on the indication of the timet0, wherein the latency comprises a first period of time from the timet0 to a transmission of the second signal from the controller unit.

In one or more sixty-eighth embodiments, further to the sixty-seventhembodiment, the power management unit to request the indication of thetime t0 comprises the power management unit to send a query to thecontroller unit, and wherein the latency further comprises a secondperiod of time during the wake-up operation, and before a communicationof the query.

In one or more sixty-ninth embodiments, further to the sixty-eighthembodiment, the latency further comprises a third period of time fromthe communication of the query to a communication of the indication ofthe time t0 to the power management unit.

In one or more seventieth embodiments, further to the sixty-ninthembodiment, the latency further comprises a fourth period of time afterthe communication of the indication of the time t0 to the powermanagement unit.

In one or more seventy-first embodiments, further to any of thesixty-fifth through seventieth embodiments, the power management unit isto send a query to the controller unit to request the indication of thetime t0, and wherein the controller unit, based on the query, is tocalculate a total time between the time t0 and a time of a communicationof the query.

In one or more seventy-second embodiments, further to any of thesixty-fifth through seventy-first embodiments, the power statetransition includes a transition of the processor from a first powerstate which disables an execution of software to a second power statewhich enables the execution of software.

In one or more seventy-third embodiments, a system comprises a processorcomprising first circuitry to detect a need to perform a power statetransition with the processor, second circuitry coupled to receive fromthe first circuitry a signal which indicates the need, wherein based onthe signal, the second circuitry is to log a time t0 of a communicationof the signal, and to generate a control signal. The processor furthercomprises third circuitry, coupled to the second circuitry, to initiatea wake-up operation in response to the control signal, request anindication of the time t0 from the second circuitry after the wake-upoperation, and provide to an operating system a communication comprisinga value, based on the indication of the time t0, which identifies alatency of the power state transition. The system further comprises adisplay device coupled to the processor, the display device to displayan image based on a signal communicated with the processor.

In one or more seventy-fourth embodiments, further to the seventy-thirdembodiment, the third circuitry is further to perform one or moreoperations of the power state transition after a receipt of theindication of the time t0 from the second circuitry.

In one or more seventy-fifth embodiments, further to the seventy-thirdembodiment or the seventy-fourth embodiment, the third circuitry is tocompute a duration of the latency based on the indication of the timet0, wherein the latency comprises a first period of time from the timet0 to a transmission of the control signal from the second circuitry.

In one or more seventy-sixth embodiments, further to the seventy-fifthembodiment, the third circuitry to request the indication of the time t0comprises the third circuitry to send a query to the second circuitry,and wherein the latency further comprises a second period of time duringthe wake-up operation, and before a communication of the query.

In one or more seventy-seventh embodiments, further to the seventy-sixthembodiment, the latency further comprises a third period of time fromthe communication of the query to a communication of the indication ofthe time t0 to the third circuitry.

In one or more seventy-eighth embodiments, further to theseventy-seventh embodiment, the latency further comprises a fourthperiod of time after the communication of the indication of the time t0to the third circuitry.

In one or more seventy-ninth embodiments, further to any of theseventy-third through seventy-eighth embodiments, the third circuitry isto send a query to the second circuitry to request the indication of thetime t0, and wherein the second circuitry, based on the query, is tocalculate a total time between the time t0 and a time of a communicationof the query.

In one or more eightieth embodiments, further to any of theseventy-third through seventy-ninth embodiments, the power statetransition includes a transition of the processor from a first powerstate which disables an execution of software to a second power statewhich enables the execution of software.

In one or more eighty-first embodiments, a method at the processorcomprises at a first circuit of the processor receiving a signal whichindicates a need to perform a power state transition with the processor,logging a time t0 of a communication of the signal, and generating acontrol signal based on the signal. The method further comprises, at asecond circuit of the processor, initiating a wake-up operation inresponse to the control signal, requesting an indication of the time t0from the first circuitry after the wake-up operation, and provide to anoperating system a communication comprising a value, based on theindication of the time t0, which identifies a latency of the power statetransition.

In one or more eighty-second embodiments, further to the eighty-firstembodiment, the second circuit is further to perform one or moreoperations of the power state transition after a receipt of theindication of the time t0 from the first circuit.

In one or more eighty-third embodiments, further to the eighty-firstembodiment or the eighty-second embodiment, the second circuit is tocompute a duration of the latency based on the indication of the timet0, wherein the latency comprises a first period of time from the timet0 to a transmission of the control signal from the first circuit.

In one or more eighty-fourth embodiments, further to the eighty-thirdembodiment, requesting the indication of the time t0 comprises thesecond circuit sending a query to the first circuit, and wherein thelatency further comprises a second period of time during the wake-upoperation, and before the sending of the query.

In one or more eighty-fifth embodiments, further to the eighty-fourthembodiment, the latency further comprises a third period of time fromthe communication of the query to a communication of the indication ofthe time t0 to the second circuit.

In one or more eighty-sixth embodiments, further to the eighty-fifthembodiment, the latency further comprises a fourth period of time afterthe communication of the indication of the time t0 to the secondcircuit.

In one or more eighty-seventh embodiments, further to any of theeighty-first through eighty-sixth embodiments, the second circuit sendsa query to the first circuit to request the indication of the time t0,and wherein the first circuit, based on the query, calculates a totaltime between the time t0 and a time of a communication of the query.

In one or more eighty-eighth embodiments, further to any of theeighty-first through eighty-seventh embodiments, the power statetransition includes a transition of the processor from a first powerstate which disables an execution of software to a second power statewhich enables the execution of software.

In one or more eighty-ninth embodiments, an integrated circuit (IC) chipcomprises an interface circuit to couple the IC chip to another IC chip,a first power management (PM) circuit coupled to the interface circuit,the first PM circuit to participate in communications with a second PMcircuit of the other IC chip while a voltage regulator is to deliverpower via a rail to each of the IC chip and the other IC chip. Thecommunications comprise a first message sent between the first PMcircuit or the second PM circuit, wherein the first message indicates afirst transition between modes of power consumption by one of the ICchip or the other IC chip, and a second message, based on the firstmessage, sent from the other of the first PM circuit or the second PMcircuit to an agent which is one of the voltage regulator or a third PMcircuit of a third IC chip, wherein the second message requests a secondtransition of a mode of power consumption or power delivery by theagent, wherein one of the first transition or the second transition isbased on the other of the first transition or the second transition.

In one or more ninetieth embodiments, further to the eighty-ninthembodiment, the first message requests a confirmation that the one ofthe first PM circuit or the second PM circuit is approved to perform thefirst transition.

In one or more ninety-first embodiments, further to the ninetiethembodiment, the agent is the voltage regulator, and wherein thecommunications further comprise a third message from the voltageregulator to the other of the first PM circuit or the second PM circuit,the third message to confirm a performance of the second transition, anda fourth message from the other of the first PM circuit or the second PMcircuit to the one of the first PM circuit or the second PM circuit, thefourth message comprising the confirmation.

In one or more ninety-second embodiments, further to the ninety-firstembodiment, the agent is the third PM circuit, wherein the secondmessage requests a performance of the second transition by the third PMcircuit, and wherein the communications further comprise a third messagefrom the third PM circuit to the other of the first PM circuit or thesecond PM circuit, the third message to confirm a performance of thesecond transition, wherein the other of the first PM circuit or thesecond PM circuit performs a third transition of a mode of powerconsumption based on the third message, and a fourth message from theother of the first PM circuit or the second PM circuit to the one of thefirst PM circuit or the second PM circuit, the fourth message comprisingthe confirmation.

In one or more ninety-third embodiments, further to any of theeighty-ninth through ninety-second embodiments, the first messageconfirms a performance of the first transition by the one of the firstPM circuit or the second PM circuit.

In one or more ninety-fourth embodiments, further to the ninety-thirdembodiment, the agent is the voltage regulator, and wherein the secondtransition is based on the first transition.

In one or more ninety-fifth embodiments, further to any of theeighty-ninth through ninety-fourth embodiments, one of the IC chip orthe other IC chip comprises the voltage regulator.

In one or more ninety-sixth embodiments, a packaged device comprises afirst integrated circuit (IC) chip comprising a first power management(PM) circuit, and a second IC chip coupled to the first IC chip, thesecond IC chip comprising a second PM circuit to participate incommunications with the first PM circuit while a voltage regulator is todeliver power via a rail to each of the first IC chip and the second ICchip. The communications comprise a first message sent between the firstPM circuit or the second PM circuit, wherein the first message indicatesa first transition between modes of power consumption by one of thefirst IC chip or the second IC chip, and a second message, based on thefirst message, sent from the other of the first PM circuit or the secondPM circuit to an agent which is one of the voltage regulator or a thirdPM circuit of a third IC chip, wherein the second message requests asecond transition of a mode of power consumption or power delivery bythe agent, wherein one of the first transition or the second transitionis based on the other of the first transition or the second transition.

In one or more ninety-seventh embodiments, further to the ninety-sixthembodiment, the first message requests a confirmation that the one ofthe first PM circuit or the second PM circuit is approved to perform thefirst transition.

In one or more ninety-eighth embodiments, further to the ninety-seventhembodiment, the agent is the voltage regulator, and wherein thecommunications further comprise a third message from the voltageregulator to the other of the first PM circuit or the second PM circuit,the third message to confirm a performance of the second transition, anda fourth message from the other of the first PM circuit or the second PMcircuit to the one of the first PM circuit or the second PM circuit, thefourth message comprising the confirmation.

In one or more ninety-ninth embodiments, further to the ninety-eighthembodiment, the agent is the third PM circuit, wherein the secondmessage requests a performance of the second transition by the third PMcircuit, and wherein the communications further comprise a third messagefrom the third PM circuit to the other of the first PM circuit or thesecond PM circuit, the third message to confirm a performance of thesecond transition, wherein the other of the first PM circuit or thesecond PM circuit performs a third transition of a mode of powerconsumption based on the third message, and a fourth message from theother of the first PM circuit or the second PM circuit to the one of thefirst PM circuit or the second PM circuit, the fourth message comprisingthe confirmation.

In one or more one hundredth embodiments, further to any of theninety-sixth through ninety-ninth embodiments, the first messageconfirms a performance of the first transition by the one of the firstPM circuit or the second PM circuit.

In one or more one hundred and first embodiments, further to the onehundredth embodiment, the agent is the voltage regulator, and whereinthe second transition is based on the first transition.

In one or more one hundred and second embodiments, further to any of theninety-sixth through one hundred and first embodiments, one of the firstIC chip or the second IC chip comprises the voltage regulator.

In one or more one hundred and third embodiments, a system comprises afirst integrated circuit (IC) chip comprising a first power management(PM) circuit, a second IC chip coupled to the first IC chip, the secondIC chip comprising a second PM circuit to participate in communicationswith the first PM circuit while a voltage regulator is to deliver powervia a rail to each of the first IC chip and the second IC chip. Thecommunications comprise a first message sent between the first PMcircuit or the second PM circuit, wherein the first message indicates afirst transition between modes of power consumption by one of the firstIC chip or the second IC chip, and a second message, based on the firstmessage, sent from the other of the first PM circuit or the second PMcircuit to an agent which is one of the voltage regulator or a third PMcircuit of a third IC chip, wherein the second message requests a secondtransition of a mode of power consumption or power delivery by theagent, wherein one of the first transition or the second transition isbased on the other of the first transition or the second transition. Thesystem further comprises a display device coupled to the first IC chip,the display device to display an image based on a signal communicatedwith the first IC chip.

In one or more one hundred and fourth embodiments, further to the onehundred and third embodiment, the first message requests a confirmationthat the one of the first PM circuit or the second PM circuit isapproved to perform the first transition.

In one or more one hundred and fifth embodiments, further to the onehundred and fourth embodiment, the agent is the voltage regulator, andwherein the communications further comprise a third message from thevoltage regulator to the other of the first PM circuit or the second PMcircuit, the third message to confirm a performance of the secondtransition, and a fourth message from the other of the first PM circuitor the second PM circuit to the one of the first PM circuit or thesecond PM circuit, the fourth message comprising the confirmation.

In one or more one hundred and sixth embodiments, further to the onehundred and fifth embodiment, the agent is the third PM circuit, whereinthe second message requests a performance of the second transition bythe third PM circuit, and wherein the communications further comprise athird message from the third PM circuit to the other of the first PMcircuit or the second PM circuit, the third message to confirm aperformance of the second transition, wherein the other of the first PMcircuit or the second PM circuit performs a third transition of a modeof power consumption based on the third message, and a fourth messagefrom the other of the first PM circuit or the second PM circuit to theone of the first PM circuit or the second PM circuit, the fourth messagecomprising the confirmation.

In one or more one hundred and seventh embodiments, further to any ofthe one hundred and third through one hundred and sixth embodiments, thefirst message confirms a performance of the first transition by the oneof the first PM circuit or the second PM circuit.

In one or more one hundred and eighth embodiments, further to the onehundred and seventh embodiment, the agent is the voltage regulator, andwherein the second transition is based on the first transition.

In one or more one hundred and ninth embodiments, further to any of theone hundred and third through one hundred and eighth embodiments, one ofthe first IC chip or the second IC chip comprises the voltage regulator.

In one or more one hundred and tenth embodiments, a method comprisesdelivering power via a rail from a voltage regulator to respectivecircuits of a first IC chip and a second IC chip, wherein a first powermanagement (PM) circuit of the first IC chip is communicatively coupledto a second PM circuit of the second IC chip, sending, from the first PMcircuit to the second PM circuit, a first message indicating a firsttransition between modes of power consumption by the first IC chip, andsending a second message, based on the first message, from the second PMcircuit to an agent which is one of the voltage regulator or a third PMcircuit of a third IC chip, wherein the second message requests a secondtransition of a mode of power consumption or power delivery by theagent, wherein one of the first transition or the second transition isbased on the other of the first transition or the second transition.

In one or more one hundred and eleventh embodiments, further to the onehundred and tenth embodiment, the first message requests a confirmationthat the first PM circuit is approved to perform the first transition.

In one or more one hundred and twelfth embodiments, further to the onehundred and eleventh embodiment, the agent is the voltage regulator, andwherein the communications further comprise a third message from thevoltage regulator to the second PM circuit, the third message to confirma performance of the second transition, and a fourth message from thesecond PM circuit to the first PM circuit, the fourth message comprisingthe confirmation.

In one or more one hundred and thirteenth embodiments, further to theone hundred and twelfth embodiment, the agent is the third PM circuit,wherein the second message requests a performance of the secondtransition by the third PM circuit, and wherein the communicationsfurther comprise a third message from the third PM circuit to the secondPM circuit, the third message to confirm a performance of the secondtransition, and wherein, based on the third message, the second PMcircuit performs a third transition of a mode of power consumption bythe second IC chip, and a fourth message from the second PM circuit tothe first PM circuit, the fourth message comprising the confirmation.

In one or more one hundred and fourteenth embodiments, further to any ofthe one hundred and tenth through one hundred and thirteenthembodiments, the first message confirms a performance of the firsttransition by the first PM circuit.

In one or more one hundred and fifteenth embodiments, further to the onehundred and fourteenth embodiment, the agent is the voltage regulator,and wherein the second transition is based on the first transition.

In one or more one hundred and sixteenth embodiments, further to any ofthe one hundred and tenth through one hundred and fifteenth embodiments,one of the first IC chip or the second IC chip comprises the voltageregulator.

In one or more one hundred and seventeenth embodiments, a devicecomprises a programmable thermal sensor to be thermally coupled to aprocessor, and circuitry coupled to the programmable thermal sensor, thecircuitry comprising a first circuit to receive reference informationwhich indicates a correspondence of thermal conditions each with adifferent respective mode of a plurality of modes of a power deliverycircuit, wherein the plurality of modes are each to deliver power to theprocessor during a power state of the processor, a second circuitcoupled to set a trigger condition of the programmable thermal sensorbased on the reference information. While the processor is in the powerstate, the programmable thermal sensor is to send a signal to thecircuitry in response to an indication that the trigger condition issatisfied, and wherein, in response to the signal and based on thereference information, the circuitry is further to control a transitionof the power delivery circuit between two of the plurality of modes, andwherein the power state is to be maintained after the transition.

In one or more one hundred and eighteenth embodiments, further to theone hundred and seventeenth embodiment, the device further comprises theprocessor.

In one or more one hundred and nineteenth embodiments, further to theone hundred and eighteenth embodiment, the device comprises anintegrated circuit chip which comprises the processor and the circuitry.

In one or more one hundred and twentieth embodiments, further to any ofthe one hundred and seventeenth through one hundred and nineteenthembodiments, the first circuit to receive the reference informationcomprises the first circuit to receive first information, from theprocessor, which indicates a correspondence of power deliveryrequirements each with a different respective one of the thermalconditions, and second information which indicates respectiveperformance characteristics of each of the plurality of modes.

In one or more one hundred and twenty-first embodiments, further to anyof the one hundred and seventeenth through one hundred and twentiethembodiments, the first circuit to receive the reference informationcomprises the first circuit to receive a value indicating an updatedperformance characteristic of one of the processor or the power deliverycircuit.

In one or more one hundred and twenty-second embodiments, further to anyof the one hundred and seventeenth through one hundred and twenty-firstembodiments, the device further comprises the power delivery circuit.

In one or more one hundred and twenty-third embodiments, further to anyof the one hundred and seventeenth through one hundred and twenty-secondembodiments, wherein the power state disables software execution withthe processor.

In one or more one hundred and twenty-fourth embodiments, a devicecomprises a thermal sensor to be thermally coupled to a processor, amanager circuit coupled to the thermal sensor, the manager circuit to becoupled to the processor and to a power delivery circuit, the managercircuit further to set a trigger condition of the thermal sensor basedon reference information which identifies multiple electrical currentrequirements of the processor as corresponding each to a differentrespective thermal condition, receive a signal from the thermal sensorduring a power state of the processor, wherein the signal indicates thata thermal condition of the processor satisfies the trigger condition,and transition the power delivery circuit, in response to the signal, toa mode of power delivery to the processor, wherein the power state is tobe maintained after the transition.

In one or more one hundred and twenty-fifth embodiments, further to theone hundred and twenty-fourth embodiment, the device further comprisesthe processor.

In one or more one hundred and twenty-sixth embodiments, further to theone hundred and twenty-fifth embodiment, the device comprises anintegrated circuit chip which comprises the processor and the managercircuit.

In one or more one hundred and twenty-seventh embodiments, further toany of the one hundred and twenty-fourth through one hundred andtwenty-sixth embodiments, the manager circuit is to receive thereference information, and wherein the reference information comprisesfirst information, from the processor, which indicates a correspondenceof power delivery requirements each with a different respective one ofthe thermal conditions, and second information which indicatesrespective performance characteristics of each of a plurality of modesof the power delivery circuit.

In one or more one hundred and twenty-eighth embodiments, further to theone hundred and twenty-seventh embodiment, the manager circuit toreceive the reference information comprises the manager circuit toreceive a value indicating an updated performance characteristic of oneof the processor or the power delivery circuit.

In one or more one hundred and twenty-ninth embodiments, further to anyof the one hundred and twenty-fourth through one hundred andtwenty-eighth embodiments, the device further comprises the powerdelivery circuit.

In one or more one hundred and thirtieth embodiments, further to any ofthe one hundred and twenty-fourth through one hundred and twenty-ninthembodiments, the power state disables software execution with theprocessor.

In one or more one hundred and thirty-first embodiments, a systemcomprises a processor, a power delivery circuit to deliver power to theprocessor, a thermal sensor thermally coupled to a processor, a managercircuit coupled to the thermal sensor and to the power delivery circuit,the manager circuit to set a trigger condition of the thermal sensorbased on reference information which identifies multiple electricalcurrent requirements of the processor as corresponding each to adifferent respective thermal condition, receive a signal from thethermal sensor during a power state of the processor, wherein the signalindicates that a thermal condition of the processor satisfies thetrigger condition, and transition the power delivery circuit, inresponse to the signal, to a mode of power delivery to the processor,wherein the power state is to be maintained after the transition. Thesystem further comprises a display device coupled to the processor, thedisplay device to display an image based on a signal communicated withthe processor.

In one or more one hundred and thirty-second embodiments, further to theone hundred and thirty-first embodiment, an integrated circuit chipcomprises the processor and the manager circuit.

In one or more one hundred and thirty-third embodiments, further to theone hundred and thirty-first embodiment or the one hundred andthirty-second embodiment, the manager circuit is to receive thereference information, and wherein the reference information comprisesfirst information, from the processor, which indicates a correspondenceof power delivery requirements each with a different respective one ofthe thermal conditions, and second information which indicatesrespective performance characteristics of each of a plurality of modesof the power delivery circuit.

In one or more one hundred and thirty-fourth embodiments, further to theone hundred and thirty-third embodiment, the manager circuit to receivethe reference information comprises the manager circuit to receive avalue indicating an updated performance characteristic of one of theprocessor or the power delivery circuit.

In one or more one hundred and thirty-fifth embodiments, further to anyof the one hundred and thirty-first through one hundred andthirty-fourth embodiments, system further comprises the power deliverycircuit.

In one or more one hundred and thirty-sixth embodiments, further to anyof the one hundred and thirty-first through one hundred and thirty-fifthembodiments, the power state disables software execution with theprocessor.

In one or more one hundred and thirty-seventh embodiments, a methodcomprises receiving, at circuitry which is coupled to a processor,reference information which indicates a correspondence of thermalconditions each with a different respective mode of a plurality of modesof a power delivery circuit, wherein the plurality of modes are each todeliver power to the processor during a power state of the processor,based on the reference information, setting a trigger condition of aprogrammable thermal sensor which is thermally coupled to the processor,after the trigger condition is set, monitoring the processor with theprogrammable thermal sensor, sending a signal from the programmablethermal sensor to the circuitry in response to an indication that thetrigger condition is satisfied, and with the circuitry, controlling atransition of the power delivery circuit between two of the plurality ofmodes, wherein the power state is maintained after the transition.

In one or more one hundred and thirty-eighth embodiments, further to theone hundred and thirty-seventh embodiment, an integrated circuit chipcomprises the processor and the circuitry.

In one or more one hundred and thirty-ninth embodiments, further to theone hundred and thirty-seventh embodiment or the one hundred andthirty-eighth embodiment, receiving the reference information comprisesthe circuitry receiving first information, from the processor, whichindicates a correspondence of power delivery requirements each with adifferent respective one of the thermal conditions, and secondinformation which indicates respective performance characteristics ofeach of the plurality of modes.

In one or more one hundred and fortieth embodiments, further to any ofthe one hundred and thirty-seventh through one hundred and thirty-ninthembodiments, receiving the reference information comprises the circuitryreceiving a value indicating an updated performance characteristic ofone of the processor or the power delivery circuit.

In one or more one hundred and forty-first embodiments, further to anyof the one hundred and thirty-seventh through one hundred and fortiethembodiments, the power state disables software execution with theprocessor.

In one or more one hundred and forty-second embodiments, a processorcomprises a first memory, a hardware interface to couple the processorto a second memory, first circuitry to receive an indication, while theprocessor is coupled to the second memory, that a transition of theprocessor to a power state is to be performed, and identify, based onthe indication, a predicted length of time that the processor is to bein the power state. The processor further comprises second circuitrycoupled to the first circuitry, the second circuitry to perform acalculation, based on the predicted length of time, to detect a relativebenefit of a storage of a state of the processor to one of the firstmemory or the second memory over a storage of the state of the processorto the other of the first memory or the second memory. The processorfurther comprises third circuitry, coupled to the second circuitry andthe hardware interface, which is to store the state of the processor,based on the calculation, to the one of the first memory or the secondmemory.

In one or more one hundred and forty-third embodiments, further to theone hundred and forty-second embodiment, the second circuitry is toperform the calculation further based on one or more of a value T1 whichis to indicate a length of time required to write a reference amount ofdata to the first memory, a value P1 which is to indicate an amount ofpower required to retain the reference amount of data in the firstmemory, a value T2 which is to indicate a length of time required towrite the reference amount of data to the second memory, a value E2which is to indicate an amount of energy required to write the referenceamount of data to the second memory and to read the reference amount ofdata from the second memory, and a value Pi which is to indicate anamount of power consumed by the processor during a reference period oftime.

In one or more one hundred and forty-fourth embodiments, further to theone hundred and forty-third embodiment, the second circuitry is toperform the calculation based on a ratio of a first value to a secondvalue, wherein the first value is based on the value Pi, and wherein thesecond value is based on the value P1.

In one or more one hundred and forty-fifth embodiments, further to theone hundred and forty-third embodiment, the first value is further basedon a difference between the value T2 and the value T1.

In one or more one hundred and forty-sixth embodiments, further to theone hundred and forty-third embodiment, the second circuitry is toperform the calculation to detect whether the predicted length of timeis less than a length of time indicated by a ratio of a first value tothe value P1, wherein the first value is based on a sum of the value E2and a second value, wherein the second value is based on a product ofthe value Pi and a difference between the values T2 and T1.

In one or more one hundred and forty-seventh embodiments, further to theone hundred and forty-sixth embodiment, the third circuitry to store thestate of the processor comprises the third circuitry to store the stateto the first memory based on an indication by the calculation that thepredicted length of time is less than the length of time indicated by aratio.

In one or more one hundred and forty-eighth embodiments, further to anyof the one hundred and forty-second through one hundred andforty-seventh embodiments, the processor further comprises fourthcircuitry to receive information communicated to the processor prior toindication, the information to indicate, for each of the first memoryand the second memory, respective resource requirements to operate thememory, wherein the second circuitry is to perform the calculationfurther based on the information.

In one or more one hundred and forty-ninth embodiments, further to theone hundred and forty-eighth embodiment, the information comprises oneor more resource requirement updates.

In one or more one hundred and fiftieth embodiments, further to any ofthe one hundred and forty-second through one hundred and forty-ninthembodiments, the first memory comprises a static random-access memory,and wherein the second memory is to comprise a dynamic random-accessmemory.

In one or more one hundred and fifty-first embodiments, one or morenon-transitory computer-readable storage media having stored thereoninstructions which, when executed by one or more processing units, causethe one or more processing units to perform a method comprisingreceiving an indication that a transition of the processor to a powerstate is to be performed, wherein the processor comprises a firstmemory, and wherein a second memory is coupled to the processor,identifying a predicted length of time that the processor is to be inthe power state, based on the indication and the predicted length oftime, performing a calculation to detect a relative benefit of storing astate of the processor to one of the first memory or the second memoryover storing the state of the processor to the other of the first memoryor the second memory, and based on the calculation, storing the state ofthe processor to the one of the first memory or the second memory.

In one or more one hundred and fifty-second embodiments, further to theone hundred and fifty-first embodiment, performing the calculation isfurther based on one or more of a value T1 indicating a length of timerequired to write a reference amount of data to the first memory, avalue P1 indicating an amount of power required to retain the referenceamount of data in the first memory, a value T2 indicating a length oftime required to write the reference amount of data to the secondmemory, a value E2 indicating an amount of energy required to write thereference amount of data to the second memory and to read the referenceamount of data from the second memory, and a value Pi indicating anamount of power consumed by the processor during a reference period oftime.

In one or more one hundred and fifty-third embodiments, further to theone hundred and fifty-second embodiment, the calculation is performedbased on a ratio of a first value to a second value, wherein the firstvalue is based on the value Pi, and wherein the second value is based onthe value P1.

In one or more one hundred and fifty-fourth embodiments, further to theone hundred and fifty-second embodiment, the first value is furtherbased on a difference between the value T2 and the value T1.

In one or more one hundred and fifty-fifth embodiments, further to theone hundred and fifty-second embodiment, the calculation is performed todetect whether the predicted length of time is less than a length oftime indicated by a ratio of a first value to the value P1, wherein thefirst value is based on a sum of the value E2 and a second value,wherein the second value is based on a product of the value Pi and adifference between the values T2 and T1.

In one or more one hundred and fifty-sixth embodiments, further to theone hundred and fifty-fifth embodiment, storing the state of theprocessor comprises storing the state to the first memory based on anindication by the calculation that the predicted length of time is lessthan the length of time indicated by a ratio.

In one or more one hundred and fifty-seventh embodiments, further to anyof the one hundred and fifty-first through one hundred and fifty-sixthembodiments, the method further comprises receiving informationcommunicated to the processor prior to indication, the informationindicating, for each of the first memory and the second memory,respective resource requirements to operate the memory, wherein thecalculation is performed further based on the information.

In one or more one hundred and fifty-eighth embodiments, further to theone hundred and fifty-seventh embodiment, the information comprises oneor more resource requirement updates.

In one or more one hundred and fifty-ninth embodiments, further to anyof the one hundred and fifty-first through one hundred and fifty-eighthembodiments, the first memory comprises a static random-access memory,and wherein the second memory comprises a dynamic random-access memory.

In one or more one hundred and sixtieth embodiments, a system comprisesa processor comprising a first memory, a hardware interface to couplethe processor to a second memory, and first circuitry to receive anindication, while the processor is coupled to the second memory, that atransition of the processor to a power state is to be performed, andidentify, based on the indication, a predicted length of time that theprocessor is to be in the power state. The processor further comprisessecond circuitry coupled to the first circuitry, the second circuitry toperform a calculation, based on the predicted length of time, to detecta relative benefit of a storage of a state of the processor to one ofthe first memory or the second memory over a storage of the state of theprocessor to the other of the first memory or the second memory. Theprocessor further comprises third circuitry, coupled to the secondcircuitry and the hardware interface, which is to store the state of theprocessor, based on the calculation, to the one of the first memory orthe second memory. The system further comprises a display device coupledto the processor, the display device to display an image based on asignal communicated with the processor.

In one or more one hundred and sixty-first embodiments, further to theone hundred and sixtieth embodiment, the second circuitry is to performthe calculation further based on one or more of a value T1 which is toindicate a length of time required to write a reference amount of datato the first memory, a value P1 which is to indicate an amount of powerrequired to retain the reference amount of data in the first memory, avalue T2 which is to indicate a length of time required to write thereference amount of data to the second memory, a value E2 which is toindicate an amount of energy required to write the reference amount ofdata to the second memory and to read the reference amount of data fromthe second memory, and a value Pi which is to indicate an amount ofpower consumed by the processor during a reference period of time.

In one or more one hundred and sixty-second embodiments, further to theone hundred and sixty-first embodiment, the second circuitry is toperform the calculation based on a ratio of a first value to a secondvalue, wherein the first value is based on the value Pi, and wherein thesecond value is based on the value P1.

In one or more one hundred and sixty-third embodiments, further to theone hundred and sixty-first embodiment, the first value is further basedon a difference between the value T2 and the value T1.

In one or more one hundred and sixty-fourth embodiments, further to theone hundred and sixty-first embodiment, the second circuitry is toperform the calculation to detect whether the predicted length of timeis less than a length of time indicated by a ratio of a first value tothe value P1, wherein the first value is based on a sum of the value E2and a second value, wherein the second value is based on a product ofthe value Pi and a difference between the values T2 and T1.

In one or more one hundred and sixty-fifth embodiments, further to theone hundred and sixty-fourth embodiment, the third circuitry to storethe state of the processor comprises the third circuitry to store thestate to the first memory based on an indication by the calculation thatthe predicted length of time is less than the length of time indicatedby a ratio.

In one or more one hundred and sixty-sixth embodiments, further to anyof the one hundred and sixtieth through one hundred and sixty-fifthembodiments, the processor further comprises fourth circuitry to receiveinformation communicated to the processor prior to indication, theinformation to indicate, for each of the first memory and the secondmemory, respective resource requirements to operate the memory, whereinthe second circuitry is to perform the calculation further based on theinformation.

In one or more one hundred and sixty-seventh embodiments, further to theone hundred and sixty-sixth embodiment, the information comprises one ormore resource requirement updates.

In one or more one hundred and sixty-eighth embodiments, further to anyof the one hundred and sixtieth through one hundred and sixty-seventhembodiments, the first memory comprises a static random-access memory,and wherein the second memory is to comprise a dynamic random-accessmemory.

In one or more one hundred and sixty-ninth embodiments, a method at aprocessor comprises receiving an indication that a transition of theprocessor to a power state is to be performed, wherein the processorcomprises a first memory, and wherein a second memory is coupled to theprocessor, identifying a predicted length of time that the processor isto be in the power state, based on the indication and the predictedlength of time, performing a calculation to detect a relative benefit ofstoring a state of the processor to one of the first memory or thesecond memory over storing the state of the processor to the other ofthe first memory or the second memory, and based on the calculation,storing the state of the processor to the one of the first memory or thesecond memory.

In one or more one hundred and seventieth embodiments, further to theone hundred and sixty-ninth embodiment, performing the calculation isfurther based on one or more of a value T1 indicating a length of timerequired to write a reference amount of data to the first memory, avalue P1 indicating an amount of power required to retain the referenceamount of data in the first memory, a value T2 indicating a length oftime required to write the reference amount of data to the secondmemory, a value E2 indicating an amount of energy required to write thereference amount of data to the second memory and to read the referenceamount of data from the second memory, and a value Pi indicating anamount of power consumed by the processor during a reference period oftime.

In one or more one hundred and seventy-first embodiments, further to theone hundred and seventieth embodiment, the calculation is performedbased on a ratio of a first value to a second value, wherein the firstvalue is based on the value Pi, and wherein the second value is based onthe value P1.

In one or more one hundred and seventy-second embodiments, further tothe one hundred and seventieth embodiment, the first value is furtherbased on a difference between the value T2 and the value T1.

In one or more one hundred and seventy-third embodiments, further to theone hundred and seventieth embodiment, the calculation is performed todetect whether the predicted length of time is less than a length oftime indicated by a ratio of a first value to the value P1, wherein thefirst value is based on a sum of the value E2 and a second value,wherein the second value is based on a product of the value Pi and adifference between the values T2 and T1.

In one or more one hundred and seventy-fourth embodiments, further tothe one hundred and seventy-third embodiment, storing the state of theprocessor comprises storing the state to the first memory based on anindication by the calculation that the predicted length of time is lessthan the length of time indicated by a ratio.

In one or more one hundred and seventy-fifth embodiments, further to anyof the one hundred and sixty-ninth through one hundred andseventy-fourth embodiments, the method further comprises receivinginformation communicated to the processor prior to indication, theinformation indicating, for each of the first memory and the secondmemory, respective resource requirements to operate the memory, whereinthe calculation is performed further based on the information.

In one or more one hundred and seventy-sixth embodiments, further to theone hundred and seventy-fifth embodiment, the information comprises oneor more resource requirement updates.

In one or more one hundred and seventy-seventh embodiments, further toany of the one hundred and sixty-ninth through one hundred andseventy-sixth embodiments, the first memory comprises a staticrandom-access memory, and wherein the second memory comprises a dynamicrandom-access memory.

In one or more one hundred and seventy-eighth embodiments, a processorcomprises first circuitry to couple the processor to multiple powergates, second circuitry to receive values which each indicate adifferent respective latency of a corresponding power gate of themultiple power gates, third circuitry to detect, after the plurality ofvalues are received, that a power state transition of the processor isto be performed, and fourth circuitry, responsive to the thirdcircuitry, to generate control signals each based on a differentrespective one or more of the values, the fourth circuitry tocommunicate the control signals each to a different respective loadcircuit of the processor, wherein, in response to the control signals,the load circuits initiate respective operations of the power statetransition at different times.

In one or more one hundred and seventy-ninth embodiments, further to theone hundred and seventy-eighth embodiment, one of the values is toreplace another value which indicates a previous latency of one of themultiple power gates.

In one or more one hundred and eightieth embodiments, further to the onehundred and seventy-eighth embodiment or the one hundred andseventy-ninth embodiment, the multiple power gates comprise first powergates and a second one or more power gates, wherein the fourth circuitryto generate the control signals comprises the fourth circuitry todetermine a first duration of a first period of time based on each offirst values which indicate respective first latencies of the firstpower gates.

In one or more one hundred and eighty-first embodiments, further to theone hundred and eightieth embodiment, the fourth circuitry to generatethe control signals further comprises the fourth circuitry to determinea second duration of a second period of time based on a second one ormore values which indicate a second one or more latencies of the secondone or more power gates.

In one or more one hundred and eighty-second embodiments, further to theone hundred and eighty-first embodiment, of the multiple power gates,the second duration is determined based a latency of only one powergate.

In one or more one hundred and eighty-third embodiments, further to theone hundred and eightieth embodiment, the fourth circuitry to determinethe first duration based on the first values comprises the fourthcircuitry to perform a calculation with the first values based on adetermination that the first plurality of power gates each belong to afirst power gate type, wherein the second one or more power gates eachbelong to a respective power gate type other than the first power gatetype.

In one or more one hundred and eighty-fourth embodiments, further to theone hundred and eightieth embodiment, the first duration is determinedbased on a maximum of the respective first latencies of the first powergates.

In one or more one hundred and eighty-fifth embodiments, further to theone hundred and eightieth embodiment, the second period of time expiresafter the first period of time, and wherein the second operation of thepower state transition is based at least in part on the first operation.

In one or more one hundred and eighty-sixth embodiments, a processorcomprises first circuitry to receive a signal while the processor iscoupled to a first power gate and to a second power gate, wherein thesignal indicates that the processor is to undergo a power statetransition, and second circuitry to determine a first duration of afirst period of time based on a first value which indicates a firstlatency of the first power gate, the second circuitry further todetermine a second duration of a second period of time based on a secondvalue which indicates a second latency of the second power gate. Theprocessor further comprises third circuitry to detect, based on thesignal, a first expiration of the first period of time, and a secondexpiration of the second period of time, wherein respective portions ofthe first period of time and the second period of time are concurrentwith each other, and fourth circuitry to signal a first circuit of theprocessor, based on the first expiration, to perform a first operationof the power state transition with power provided via the first powergate, the fourth circuitry further to signal a second circuit of theprocessor, based on the second expiration, to perform a second operationof the power state transition with power provided via the second powergate.

In one or more one hundred and eighty-seventh embodiments, further tothe one hundred and eighty-sixth embodiment, the second circuitry is tostore data communicated to the processor by an external agent prior tothe signal, wherein the data comprises the first value and the secondvalue.

In one or more one hundred and eighty-eighth embodiments, further to theone hundred and eighty-seventh embodiment, one of the first value or thesecond value are to replace another value which indicates a previouslatency of one of the first power gate or the second power gate.

In one or more one hundred and eighty-ninth embodiments, further to anyof the one hundred and eighty-sixth through one hundred andeighty-eighth embodiments, the signal is to be received while theprocessor is coupled to a first plurality of power gates comprising thefirst power gate, wherein the second circuitry is to determine the firstduration based on a first plurality of values which indicate firstlatencies each of a different respective one of the first plurality ofpower gates.

In one or more one hundred and ninetieth embodiments, further to the onehundred and eighty-ninth embodiment, the second circuitry to determinethe first duration based on the first value includes the secondcircuitry to perform a calculation with the first plurality of valuesbased on a determination that the first plurality of power gates eachbelong to a first power gate type, wherein the second power gate belongsto a second power gate type other than the first power gate type.

In one or more one hundred and ninety-first embodiments, further to theone hundred and eighty-ninth embodiment, the first duration isdetermined based on a maximum of the first latencies.

In one or more one hundred and ninety-second embodiments, further to theone hundred and ninety-first embodiment, the second duration isdetermined independent of any value which indicates a latency of a powergate other than the second power gate.

In one or more one hundred and ninety-third embodiments, further to theone hundred and eighty-ninth embodiment, the second period of timeexpires after the first period of time, and wherein the second operationof the power state transition is based at least in part on the firstoperation.

In one or more one hundred and ninety-fourth embodiments, a systemcomprises multiple power gates, and a processor coupled to the multiplepower gates, the processor comprising first circuitry to receive valueswhich each indicate a different respective latency of a correspondingpower gate of the multiple power gates, second circuitry to detect,after the plurality of values are received, that a power statetransition of the processor is to be performed, and third circuitry,responsive to the second circuitry, to generate control signals eachbased on a different respective one or more of the values, the thirdcircuitry to communicate the control signals each to a differentrespective load circuit of the processor, wherein, in response to thecontrol signals, the load circuits initiate respective operations of thepower state transition at different times. The system further comprisesa display device coupled to the processor, the display device to displayan image based on a signal communicated with the processor.

In one or more one hundred and ninety-fifth embodiments, further to theone hundred and ninety-fourth embodiment, one of the values is toreplace another value which indicates a previous latency of one of themultiple power gates.

In one or more one hundred and ninety-sixth embodiments, further to theone hundred and ninety-fourth embodiment or the one hundred andninety-fifth embodiment, the multiple power gates comprise first powergates and a second one or more power gates, wherein the third circuitryto generate the control signals comprises the third circuitry todetermine a first duration of a first period of time based on each offirst values which indicate respective first latencies of the firstpower gates.

In one or more one hundred and ninety-seventh embodiments, further tothe one hundred and ninety-sixth embodiment, the third circuitry togenerate the control signals further comprises the third circuitry todetermine a second duration of a second period of time based on a secondone or more values which indicate a second one or more latencies of thesecond one or more power gates.

In one or more one hundred and ninety-eighth embodiments, further to theone hundred and ninety-seventh embodiment, of the multiple power gates,the second duration is determined based a latency of only one powergate.

In one or more one hundred and ninety-ninth embodiments, further to theone hundred and ninety-sixth embodiment, the third circuitry todetermine the first duration based on the first values comprises thethird circuitry to perform a calculation with the first values based ona determination that the first plurality of power gates each belong to afirst power gate type, wherein the second one or more power gates eachbelong to a respective power gate type other than the first power gatetype.

In one or more two hundredth embodiments, further to the one hundred andninety-sixth embodiment, the first duration is determined based on amaximum of the respective first latencies of the first power gates.

In one or more two hundred and first embodiments, further to the onehundred and ninety-sixth embodiment, the second period of time expiresafter the first period of time, and wherein the second operation of thepower state transition is based at least in part on the first operation.

In one or more two hundred and second embodiments, a method at aprocessor comprises receiving values which each indicate a differentrespective latency of a corresponding power gate of the multiple powergates which are coupled to the processor, after receiving the pluralityof values, detecting that a power state transition of the processor isto be performed, based on the detecting, generating control signal eachbased on a different respective one or more of the values, andcommunicating the control signals each to a different respective loadcircuit of the processor, wherein, in response to the control signals,the load circuits initiate respective operations of the power statetransition at different times.

In one or more two hundred and third embodiments, further to the twohundred and second embodiment, one of the values is to replace anothervalue indicating a previous latency of one of the multiple power gates.

In one or more two hundred and fourth embodiments, further to the twohundred and second embodiment or the two hundred and third embodiment,the multiple power gates comprises first power gates and a second one ormore power gates, wherein generating the control signals comprisesdetermining a first duration of a first period of time based on each offirst values which indicate respective first latencies of the firstpower gates.

In one or more two hundred and fifth embodiments, further to the twohundred and fourth embodiment, generating the control signals furthercomprises determining a second duration of a second period of time basedon a second one or more values which indicate a second one or morelatencies of the second one or more power gates.

In one or more two hundred and sixth embodiments, further to the twohundred and fifth embodiment, of the multiple power gates, the secondduration is determined based a latency of only one power gate.

In one or more two hundred and seventh embodiments, further to the twohundred and fourth embodiment, determining the first duration based onthe first values includes performing a calculation with the first valuesbased on a determination that the first plurality of power gates eachbelong to a first power gate type, wherein the second one or more powergates each belong to a respective power gate type other than the firstpower gate type.

In one or more two hundred and eighth embodiments, further to the twohundred and fourth embodiment, the first duration is determined based ona maximum of the respective first latencies of the first power gates.

In one or more two hundred and ninth embodiments, further to the twohundred and fourth embodiment, the second period of time expires afterthe first period of time, and wherein the second operation of the powerstate transition is based at least in part on the first operation.

Besides what is described herein, various modifications may be made tothe disclosed embodiments and implementations thereof without departingfrom their scope. Therefore, the illustrations and examples hereinshould be construed in an illustrative, and not a restrictive sense. Thescope of the invention should be measured solely by reference to theclaims that follow.

What is claimed is:
 1. A processor apparatus, comprising: a controllerunit to receive a first signal comprising an indication of a need toperform a power state transition with the processor, and log a time t0of a communication of the first signal; and a power management unitcoupled to receive from the controller unit a second signal based on theindication. The power management unit to perform a wake-up operation inresponse to the second signal, determine the time t0 from the controllerunit after the wake-up operation, and based on the time t0, to generatean output comprising an identifier of a latency of the power statetransition.
 2. The apparatus of claim 1, wherein the power managementunit is further to perform one or more operations of the power statetransition after a receipt of the indication of the time t0 from thecontroller unit.
 3. The apparatus of claim 2, wherein the powermanagement unit is to compute a duration of the latency based on theindication of the time t0, wherein the latency comprises a first periodof time from the time t0 to a transmission of the second signal from thecontroller unit.
 4. The apparatus of claim 3, wherein the powermanagement unit is to request the indication of the time t0, wherein indoing so, the power management unit is to send a query to the controllerunit, and wherein the latency further comprises a second period of timeduring the wake-up operation, and before a communication of the query.5. The apparatus of claim 4, wherein the latency further comprises athird period of time from the communication of the query to acommunication of the indication of the time t0 to the power managementunit.
 6. The apparatus of claim 5, wherein, the latency furthercomprises a fourth period of time after the communication of theindication of the time t0 to the power management unit.
 7. The apparatusof claim 1, wherein the power management unit is to send a query to thecontroller unit to request the indication of the time t0, and whereinthe controller unit, based on the query, is to calculate a total timebetween the time t0 and a time of a communication of the query.
 8. Theapparatus of claim 1, wherein the power state transition includes atransition of the processor from a first power state which is to disablean execution of software to a second power state which is to enable theexecution of software.
 9. A system, comprising: a processor including:first circuitry to detect a need to perform a power state transitionwith the processor, second circuitry coupled to receive from the firstcircuitry a signal which indicates the need, wherein based on thesignal, the second circuitry is to log a time t0 of a communication ofthe signal, and to generate a control signal, and third circuitry,coupled to the second circuitry, to initiate a wake-up operation inresponse to the control signal, request an indication of the time t0from the second circuitry after the wake-up operation, and provide to anoperating system a communication comprising a value, based on theindication of the time t0, identifying a latency of the power statetransition; and a display device coupled to the processor, the displaydevice to display an image based on a signal communicated with theprocessor.
 10. The system of claim 9, wherein the third circuitry is toperform one or more operations of the power state transition after areceipt of the indication of the time t0 from the second circuitry. 11.The system of claim 9, wherein the third circuitry is to compute aduration of the latency based on the indication of the time t0, whereinthe latency comprises a first period of time from the time t0 to atransmission of the control signal from the second circuitry.
 12. Thesystem of claim 11, wherein the third circuitry is to request theindication of the time t0, the request includes the third circuitry tosend a query to the second circuitry, and wherein the latency furthercomprises a second period of time during the wake-up operation, andbefore a communication of the query.
 13. The system of claim 12, whereinthe latency further comprises a third period of time from thecommunication of the query to a communication of the indication of thetime t0 to the third circuitry.
 14. The system of claim 13, wherein thelatency further comprises a fourth period of time after thecommunication of the indication of the time t0 to the third circuitry.15. The system of claim 9, wherein the third circuitry is to send aquery to the second circuitry to request the indication of the time t0,and wherein the second circuitry, based on the query, is to calculate atotal time between the time t0 and a time of a communication of thequery.
 16. The system of claim 9, wherein the power state transitionincludes a transition of the processor from a first power state whichdisables an execution of software to a second power state which enablesthe execution of software.
 17. A method, comprising: at a firstprocessor circuit: receiving a signal which indicates a need to performa power state transition with the processor, logging a time t0 of acommunication of the signal, and generating a control signal based onthe signal; and at a second processor circuit: initiating a wake-upoperation in response to the control signal, requesting an indication ofthe time t0 from the first circuit after the wake-up operation, andproviding to an operating system a communication comprising a value,based on the indication of the time t0 that identifies a latency of thepower state transition.
 18. The method of claim 17, wherein the secondcircuit is to further perform one or more operations of the power statetransition after a receipt of the indication of the time t0 from thefirst circuit.
 19. The method of claim 17, wherein the second circuit isto compute a duration of the latency based on the indication of the timet0, wherein the latency comprises a first period of time from the timet0 to a transmission of the control signal from the first circuit. 20.The method of claim 19, wherein requesting the indication of the time t0comprises the second circuit sending a query to the first circuit, andwherein the latency further comprises a second period of time during thewake-up operation and before the sending of the query.